Hi Sylwester,

On Tuesday 31 July 2012 14:38:35 Sylwester Nawrocki wrote:

On 07/31/2012 01:05 PM, Laurent Pinchart wrote:

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What about CSI receivers that can reroute the lanes internally ? We
would need to specify lane indices for each lane then, maybe with
something like

clock-lane =<0>;
data-lanes =<2 3 1>;

Sounds good to me. And the clock-lane could be made optional, as not
all devices would need it.

However, as far as I can see, there is currently no generic API for
handling this kind of data structure. E.g. number of cells for the
"interrupts" property is specified with an additional
"#interrupt-cells" property.

It would have been much easier to handle something like:

data-lanes = <2>, <3>, <1>;

i.e. an array of the lane indexes.

I'm fine with that.

...on a second thought: shouldn't this be handled by pinctrl? Or is it
some CSI-2 module internal lane switching, not the global SoC pin
function configuration?

On the hardware I came across, it's handled by the CSI2 receiver, not the
SoC pinmux feature.

Same here. Is there any hardware known to mux those MIPI-CSI
D-PHY high speed differential signals with general purpose IO pins ?

Or are there mostly dedicated pins used ?

The OMAP3 multiplexes the CSI pins with other functions.

However, if there are cases the lane configuration is done solely at CSI2
receiver level, there seems little point in involving the pinctrl API.

The OMAP3 handles lane routing in the CSI2 receiver.

-- 
Regards,

Laurent Pinchart