Re: [PATCH v3 4/4] i2c: i2c-ocores: support for 16bit and 32bit IO

On Fri, Jul 13, 2012 at 07:18:35PM +0530, Shubhrajyoti Datta wrote:

Hello,

On Fri, Jul 13, 2012 at 7:14 PM, Jayachandran C
[off-list ref] wrote:

quoted

From: Ganesan Ramalingam <ganesanr-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>

Some architectures supports only 16-bit or 32-bit read/write access to
their IO space. Add a 'reg-io-width' platform and OF parameter which
specifies the IO width to support these platforms.

reg-io-width can be specified as 1, 2 or 4, and has a default value
of 1 if it is unspecified.

Signed-off-by: Ganesan Ramalingam <ganesanr-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Signed-off-by: Jayachandran C <jayachandranc-oSioyQM9ZPnuBjGU1YDckgC/G2K4zDHf@public.gmane.org>
---
 .../devicetree/bindings/i2c/i2c-ocores.txt         |    2 ++
 drivers/i2c/busses/i2c-ocores.c                    |   21 ++++++++++++++++++--
 include/linux/i2c-ocores.h                         |    1 +
 3 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
index 1c9334b..c15781f 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt

@@ -10,6 +10,7 @@ Required properties:

 Optional properties:
 - reg-shift       : device register offsets are shifted by this value
+- reg-io-width    : io register width in bytes (1, 2 or 4)
 - regstep         : deprecated, use reg-shift above

 Example:

@@ -23,6 +24,7 @@ Example:
                clock-frequency = <20000000>;

                reg-shift = <0>;        /* 8 bit registers */
+               reg-io-width = <1>;     /* 8 bit read/write */

                dummy@60 {
                        compatible = "dummy";

diff --git a/drivers/i2c/busses/i2c-ocores.c b/drivers/i2c/busses/i2c-ocores.c
index 721ead9..de3b119 100644
--- a/drivers/i2c/busses/i2c-ocores.c
+++ b/drivers/i2c/busses/i2c-ocores.c

@@ -30,6 +30,7 @@
 struct ocores_i2c {
        void __iomem *base;
        u32 reg_shift;
+       u32 reg_io_width;
        wait_queue_head_t wait;
        struct i2c_adapter adap;
        struct i2c_msg *msg;

@@ -72,12 +73,22 @@ struct ocores_i2c {

 static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
 {
-       iowrite8(value, i2c->base + (reg << i2c->reg_shift));
+       if (i2c->reg_io_width == 4)
+               iowrite32(value, i2c->base + (reg << i2c->reg_shift));
+       else if (i2c->reg_io_width == 2)
+               iowrite16(value, i2c->base + (reg << i2c->reg_shift));
+       else
+               iowrite8(value, i2c->base + (reg << i2c->reg_shift));
 }

 static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)

Should the return type be changed.
Now that it is returning more that than 8 bits.

Did I miss something?

Only 8 bits of the register is significant, so even if we read 16 or 32
bits only the lowest 8 bits are returned.

JC.