Thread (10 messages) flat view 10 messages, 4 authors, 2012-06-11

Re: [PATCH 1/2] edac: add support for Calxeda highbank memory controller

From: Borislav Petkov <hidden>
Date: 2012-06-07 12:44:38
Also in: lkml

On Wed, Jun 06, 2012 at 05:56:40PM -0500, Rob Herring wrote:
quoted
Hmm... I suspect that memories by DIMM chip select/channel at Calxeda,
as it is using just 1 cs/channel. It probably makes more sense to add new layer
type(s) to properly represent the way your memory controller addresses it, if
Calxeda doesn't work with DIMMs.
Not sure I follow. DIMMs are supported, but only a newer JEDEC form
factor (DDR3 72-bit mini DIMM). The h/w pretty much fixed to a single
4GB DIMM. The controller is 1 72-bit channel.
Me too, why would this need a new define although those are more-or-less
normal DIMMs (modulo the form factor)?

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Boris.

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