Re: Device tree FSL description for Microblaze

On Wed, Jul 13, 2011 at 1:12 AM, Grant Likely [off-list ref]wrote:

On Tue, Jul 12, 2011 at 3:30 PM, Michal Simek [off-list ref] wrote:

quoted

Any comments on this?

Sorry I didn't comment, but this is the first I've seen it.  I missed
it the first time around.

It's hard to provide any useful comments on this.  I have no idea what
FSL devices are.

FSL is a point-to-point FIFO bus architecture.  MicroBlaze has native ports
on the CPU that allow direct connection to up to 16 master / slave pairs of
these buses.

It's equivalent in some senses to the AXI streaming protocol - indeed newer
MicroBlaze versions can talk AXI stream, and it will also have a role in the
Zynq architecture.

FSL / AXI stream is a bit wierd from a device tree point of view - they are
point to point, unidirectional buses - FIFOs basically.  Completely
different from your standard shared SoC bus.

We are looking for a good way to express this topology in the device tree.
It is important to get this right - FSL and AXI stream will be an
increasingly important way of connecting coprocessors and devices within
Xilinx MicroBlaze and Zynq systems.  We'd like to get consensus now rather
than finding opposition 6-12 months from now when we try to push stuff that
we've already shipped.

Thanks,

John
-- 
John Williams, PhD, B. Eng, B. IT
PetaLogix - Linux Solutions for a Reconfigurable World
w: www.petalogix.com  p: +61-7-30090663  f: +61-7-30090663