linux-cxl archive · May 2021

124 messages across 20 threads, ordered by last activity .

• STALE1823d LANDED [PATCH] cxl/pci: Fixup devm_cxl_iomap_block() to take a 'struct device *'
  2021-05-28 11:12 · 1 reply this month · Dan Williams <hidden>
• STALE1820d [PATCH V3 0/5] Map register blocks individually
  2021-05-28 00:49 · 5 replies this month · ira.weiny@intel.com
• STALE1829d [PATCH v2 0/5] Map register blocks individually
  2021-05-27 17:53 · 11 replies this month · ira.weiny@intel.com
• STALE1830d [PATCH] cxl: Rename mem to pci
  2021-05-26 18:01 · 5 replies this month · Ben Widawsky <hidden>
• STALE1787d [PATCH v4 0/5] PCI Data Object Exchange support + CXL CDAT
  2021-05-25 10:27 · 6 replies this month · Jonathan Cameron <Jonathan.Cameron@huawei.com>
• STALE1836d [PATCH 0/7] Enumerate HDM Decoder registers
  2021-05-20 21:30 · 1 reply this month · Ben Widawsky <hidden>
• STALE1836d LANDED [PATCH] cxl/mem: Demarcate vendor specific capability IDs
  2021-05-20 20:55 · 1 reply this month · Ben Widawsky <hidden>
• STALE1836d LANDED [PATCH] cxl/docs: Fix "Title underline too short" warning
  2021-05-20 19:54 · 1 reply this month · Dan Williams <hidden>
• STALE1836d LANDED [PATCH] cxl/pci.c: Add a 'label_storage_size' attribute to the memdev
  2021-05-20 19:50 · 1 reply this month · Vishal Verma <vishal.l.verma@intel.com>
• STALE1836d [PATCH 0/4] Map register blocks individually
  2021-05-20 19:44 · 9 replies this month · ira.weiny@intel.com
• STALE1814d CXL Vendor Specific Capabilities
  2021-05-20 11:57 · 2 replies this month · <hidden>
• STALE1837d [RFC PATCH v3 0/4] PCI Data Object Exchange support + CXL CDAT
  2021-05-20 08:23 · 26 replies this month · Jonathan Cameron <Jonathan.Cameron@huawei.com>
• STALE1837d LANDED [PATCH 1/3] cxl/mem: Fix register block offset calculation
  2021-05-19 20:01 · 1 reply this month · Ben Widawsky <hidden>
• STALE1839d Access to CXL memory
  2021-05-18 02:01 · 1 reply this month · Dengcheng Zhu <hidden>
• STALE1821d Re: [RFC PATCH] Documentation/arm64: describe the kernel's expectations of 'memory'
  2021-05-17 12:29 · 3 replies this month · Jonathan Cameron <Jonathan.Cameron@Huawei.com>
• STALE1842d [PATCH v4 0/8] CXL Port Enumeration and Plans for v5.14
  2021-05-14 22:54 · 12 replies this month · Dan Williams <hidden>
• STALE1845d [PATCH v3 0/8] CXL Port Enumeration and Plans for v5.14
  2021-05-12 06:36 · 21 replies this month · Dan Williams <hidden>
• DORMANTno replies Personal
  2021-05-10 19:37 · 0 replies this month · Chris Pavlides <hidden>
• DORMANTno replies CXL HDM alignment
  2021-05-07 01:47 · 0 replies this month · Dai WeiBin (David Dai) <hidden>
• DORMANTno replies Get back To Me
  2021-05-01 11:56 · 0 replies this month · Madudu <hidden>