Thread (24 messages) 24 messages, 3 authors, 2019-08-30

Re: [PATCH v8 13/16] crypto: caam - select DMA address size at runtime

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From: Andrey Smirnov <hidden>
Date: 2019-08-20 20:29:21
Also in: lkml

On Tue, Aug 20, 2019 at 1:24 PM Andrey Smirnov [off-list ref] wrote:
quoted hunk ↗ jump to hunk
i.MX8 mScale SoC still use 32-bit addresses in its CAAM implmentation,
so we can't rely on sizeof(dma_addr_t) to detemine CAAM pointer
size. Convert the code to query CTPR and MCFGR for that during driver
probing.

Signed-off-by: Andrey Smirnov <redacted>
Cc: Chris Spencer <redacted>
Cc: Cory Tusar <redacted>
Cc: Chris Healy <redacted>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Horia Geantă <horia.geanta@nxp.com>
Cc: Aymen Sghaier <redacted>
Cc: Leonard Crestez <redacted>
Cc: linux-crypto@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
 drivers/crypto/caam/caampkc.c     |  8 +++----
 drivers/crypto/caam/ctrl.c        |  5 +++-
 drivers/crypto/caam/desc_constr.h | 10 ++++++--
 drivers/crypto/caam/intern.h      |  2 +-
 drivers/crypto/caam/pdb.h         | 16 +++++++++----
 drivers/crypto/caam/pkc_desc.c    |  8 +++----
 drivers/crypto/caam/regs.h        | 40 +++++++++++++++++++++++--------
 7 files changed, 63 insertions(+), 26 deletions(-)
diff --git a/drivers/crypto/caam/caampkc.c b/drivers/crypto/caam/caampkc.c
index 5b12b232ee5e..83f96d4f86e0 100644
--- a/drivers/crypto/caam/caampkc.c
+++ b/drivers/crypto/caam/caampkc.c
@@ -17,13 +17,13 @@
 #include "sg_sw_sec4.h"
 #include "caampkc.h"

-#define DESC_RSA_PUB_LEN       (2 * CAAM_CMD_SZ + sizeof(struct rsa_pub_pdb))
+#define DESC_RSA_PUB_LEN       (2 * CAAM_CMD_SZ + SIZEOF_RSA_PUB_PDB)
 #define DESC_RSA_PRIV_F1_LEN   (2 * CAAM_CMD_SZ + \
-                                sizeof(struct rsa_priv_f1_pdb))
+                                SIZEOF_RSA_PRIV_F1_PDB)
 #define DESC_RSA_PRIV_F2_LEN   (2 * CAAM_CMD_SZ + \
-                                sizeof(struct rsa_priv_f2_pdb))
+                                SIZEOF_RSA_PRIV_F2_PDB)
 #define DESC_RSA_PRIV_F3_LEN   (2 * CAAM_CMD_SZ + \
-                                sizeof(struct rsa_priv_f3_pdb))
+                                SIZEOF_RSA_PRIV_F3_PDB)
 #define CAAM_RSA_MAX_INPUT_SIZE        512 /* for a 4096-bit modulus */

 /* buffer filled with zeros, used for padding */
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 47b92451756f..4b7f95f64e34 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -602,7 +602,10 @@ static int caam_probe(struct platform_device *pdev)
        caam_imx = (bool)imx_soc_match;

        comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);
-       caam_ptr_sz = sizeof(dma_addr_t);
+       if (comp_params & CTPR_MS_PS && rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR)
Horia:

As I previously mentioned, i.MX8MQ SRM I have doesn't document MCFGR
bits related to this. If you don't mind, please double check that
using MCFGR_LONG_PTR here is correct.

Thanks,
Andrey Smirnov
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