[PATCH 13/40] mfd: ti_am335x_tscadc: Reword the comment explaining the dividers
From: Miquel Raynal <miquel.raynal@bootlin.com>
Date: 2021-08-25 15:32:43
Also in:
linux-devicetree, linux-iio, linux-input, linux-omap
Subsystem:
multifunction devices (mfd), the rest · Maintainers:
Lee Jones, Linus Torvalds
The comment misses the main information which is that we assume that a sample takes 15 ADC clock cycles to be generated. Let's take the occasion to rework a little bit this comment. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> --- drivers/mfd/ti_am335x_tscadc.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/mfd/ti_am335x_tscadc.c b/drivers/mfd/ti_am335x_tscadc.c
index 0fef35e1e64b..3afe22680973 100644
--- a/drivers/mfd/ti_am335x_tscadc.c
+++ b/drivers/mfd/ti_am335x_tscadc.c@@ -195,12 +195,12 @@ static int ti_tscadc_probe(struct platform_device *pdev) pm_runtime_get_sync(&pdev->dev); /* - * The TSC_ADC_Subsystem has 2 clock domains - * OCP_CLK and ADC_CLK. - * The ADC clock is expected to run at target of 3MHz, - * and expected to capture 12-bit data at a rate of 200 KSPS. - * The TSC_ADC_SS controller design assumes the OCP clock is - * at least 6x faster than the ADC clock. + * The TSC_ADC_Subsystem has 2 clock domains: OCP_CLK and ADC_CLK. + * ADCs produce a 12-bit sample every 15 ADC_CLK cycles. + * am33xx ADCs expect to capture 200ksps. + * We need the ADC clocks to run at 3MHz. + * This frequency is valid since TSC_ADC_SS controller design + * assumes the OCP clock is at least 6x faster than the ADC clock. */ clk = devm_clk_get(&pdev->dev, "adc_tsc_fck"); if (IS_ERR(clk)) {
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2.27.0