Hi Fabio,

On Thu, 2021-08-26 at 17:10 -0300, Fabio Estevam wrote:

Hi Stefan,

On Thu, Aug 26, 2021 at 12:20 PM Stefan Riedmueller
[off-list ref] wrote:

quoted

According to the imx6ul Reference Manual the csi clk gate register is
CCM_CCGR3 (offset 0x74) bit 0/1. For the imx6ull on the other hand the
Reference Manual lists register CCM_CCGR2 (offset 0x70) bit 2/3 as the
csi clk gate which is the current setting.

Tests have shown though that the correct csi clk gate register for the
imx6ull is actually CCM_CCGR3 bit 0/1 as well. Thus set the correct
register for both platforms.

Signed-off-by: Stefan Riedmueller <redacted>

I tested the series on an imx6ull-evk with an OV5640 sensor:

Tested-by: Fabio Estevam <festevam@gmail.com>

but in my case, I did not see the problem even without your patch.

Most likely because the bootloader turned on the CSI clock.

thanks for your testing and review.

You're right, the csi clock is enabled by default and thus the issue only
arises when you try to disable the clock e.g. to save power on a connected
sensor.

quoted

---
 drivers/clk/imx/clk-imx6ul.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index 206e4c43f68f..5dd222fab01b 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c

@@ -380,7 +380,6 @@ static void __init imx6ul_clocks_init(struct

device_node *ccm_node)
                hws[IMX6ULL_CLK_ESAI_IPG]       =
imx_clk_hw_gate2_shared("esai_ipg",   "ahb",          base + 0x70,    0,
&share_count_esai);
                hws[IMX6ULL_CLK_ESAI_MEM]       =
imx_clk_hw_gate2_shared("esai_mem",   "ahb",          base + 0x70,    0,
&share_count_esai);
        }
-       hws[IMX6UL_CLK_CSI]             =
imx_clk_hw_gate2("csi",               "csi_podf",             base +
0x70,    2);
        hws[IMX6UL_CLK_I2C1]            =
imx_clk_hw_gate2("i2c1",              "perclk",       base + 0x70,    6);
        hws[IMX6UL_CLK_I2C2]            =
imx_clk_hw_gate2("i2c2",              "perclk",       base + 0x70,    8);
        hws[IMX6UL_CLK_I2C3]            =
imx_clk_hw_gate2("i2c3",              "perclk",       base + 0x70,    10);

@@ -391,6 +390,7 @@ static void __init imx6ul_clocks_init(struct

device_node *ccm_node)
        hws[IMX6UL_CLK_PXP]             =
imx_clk_hw_gate2("pxp",               "axi",          base + 0x70,    30);

        /* CCGR3 */

It would be nice to put a comment here explaining the imx6ull
Reference Manual mismatch.

Sure I will prepare something.

Maybe Abel could help to check internally at NXP?

Yes, that would be nice!

Regards,
Stefan

quoted

+       hws[IMX6UL_CLK_CSI]             =
imx_clk_hw_gate2("csi",       "csi_podf",     base + 0x74,    0);

Thanks