On Tue 29 Jun 08:36 CDT 2021, Shawn Guo wrote:

On Sun, Jun 27, 2021 at 05:28:34PM -0700, Stephen Boyd wrote:

quoted

Quoting Shawn Guo (2021-05-03 22:28:42)

quoted

Unlike MSM8916 which has only one APCS clock, MSM8939 gets three for
Cluster0 (little cores), Cluster1 (big cores) and CCI (Cache Coherent
Interconnect).  Instead of hard coding APCS (and A53PLL) clock name,
retrieve the name from DT, so that multiple APCS clocks can be
registered.

Signed-off-by: Shawn Guo <redacted>
---
 drivers/clk/qcom/a53-pll.c      | 5 ++++-
 drivers/clk/qcom/apcs-msm8916.c | 5 ++++-
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/a53-pll.c b/drivers/clk/qcom/a53-pll.c
index 8614b0b0e82c..964f5ab7d02f 100644
--- a/drivers/clk/qcom/a53-pll.c
+++ b/drivers/clk/qcom/a53-pll.c

@@ -42,6 +42,7 @@ static int qcom_a53pll_probe(struct platform_device *pdev)
        struct clk_pll *pll;
        void __iomem *base;
        struct clk_init_data init = { };
+       const char *clk_name = NULL;
        int ret;
 
        pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);

@@ -66,7 +67,9 @@ static int qcom_a53pll_probe(struct platform_device *pdev)
        pll->status_bit = 16;
        pll->freq_tbl = a53pll_freq;
 
-       init.name = "a53pll";
+       of_property_read_string(pdev->dev.of_node, "clock-output-names",
+                               &clk_name);

Please no? Is there any use for this? Why not just generate the name as
a53pll@<MMIO ADDRESS>?

There is no other use for this than getting different names.  I will do
what you suggest here.  Thanks!

I have exactly the same problem with my two DP PHYs (in
phy_dp_clks_register()), so I'm in favor of us setting some sort of
standard for this (not for anyone to rely on, but to avoid everyone
coming up with their own scheme).

But unfortunately I don't have easy access to the phy block's base
address in phy_dp_clks_register().

Regards,
Bjorn

Shawn

quoted

quoted

+       init.name = clk_name ? clk_name : "a53pll";
        init.parent_names = (const char *[]){ "xo" };
        init.num_parents = 1;
        init.ops = &clk_pll_sr2_ops;