Re: [PATCH 2/5] clk: renesas: r8a779a0: add clocks for RAVB
From: Geert Uytterhoeven <geert@linux-m68k.org>
Date: 2021-01-05 15:22:50
Also in:
linux-renesas-soc, lkml
Hi Wolfram, On Sun, Dec 27, 2020 at 2:04 PM Wolfram Sang [off-list ref] wrote:
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Thanks for your patch!
quoted hunk ↗ jump to hunk
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c@@ -148,6 +148,12 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { }; static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { + DEF_MOD("avb0", 211, R8A779A0_CLK_S3D1), + DEF_MOD("avb1", 212, R8A779A0_CLK_S3D1), + DEF_MOD("avb2", 213, R8A779A0_CLK_S3D1), + DEF_MOD("avb3", 214, R8A779A0_CLK_S3D1), + DEF_MOD("avb4", 215, R8A779A0_CLK_S3D1), + DEF_MOD("avb5", 216, R8A779A0_CLK_S3D1),
For all other SoCs, we used the HP clock (S3D2 on R-Car V3U) instead of the ZS clock as the parent clock of the EtherAVB module clocks. Hence I think we should be consequent and use S3D2 here.
DEF_MOD("csi40", 331, R8A779A0_CLK_CSI0),
DEF_MOD("csi41", 400, R8A779A0_CLK_CSI0),
DEF_MOD("csi42", 401, R8A779A0_CLK_CSI0),
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds