Hi,

Am Mittwoch, 16. September 2015, 11:30:26 schrieb Jaehoon Chung:

On 09/16/2015 07:09 AM, Heiko St=FCbner wrote:

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Am Dienstag, 15. September 2015, 17:25:38 schrieb Jaehoon Chung:

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On 09/01/2015 03:24 AM, Heiko Stuebner wrote:

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From: Alexandru M Stan <redacted>
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This algorithm will try 1 degree increments, since there's no way=

 to

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tell
what resolution the underlying phase code uses. As an added bonus=

, doing

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many tunings yields better results since some tests are run more =

than

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once
(ex: if the underlying driver uses 45 degree increments, the tuni=

ng code

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will try the same angle more than once).
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It will then construct a list of good phase ranges (even ranges t=

hat

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cross
360/0), will pick the biggest range then it will set the sample_c=

lk to

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the
middle of that range.
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We do not touch ciu_drive (and by extension define default-drive-=

phase).

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Drive phase is mostly used to define minimum hold times, while on=

e could

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write some code to determine what phase meets the minimum hold ti=

me (ex

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10
degrees) this will not work with the current clock phase framewor=

k

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(which
floors angles, so we'll get 0 deg, and there's no way to know wha=

t

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resolution the floors happen at). We assume that the default driv=

e

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angles
set by the hardware are good enough.
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If a device has device specific code (like exynos) then that will=

 still

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take precedence, otherwise this new code will execute. If the dev=

ice

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wants
to tune, but has no sample_clk defined we'll return EIO with an e=

rror

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message.

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Which point is "_generic_"? I don't find the code that control the=

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register
relevant to CLK_DRV/SMPL PHASE. It seems that posted the similar p=

atches

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at
u-boot mailing list..

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The "generic" part is that it uses the clk phase API for dw_mmc
implementations where the clkgen controlling interface is outside t=

he

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dw_mmc IP itself. So it's open for other implementations as well.

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Designware IP also has the CLK phase register(UHS_REG_EXT register)..=

.

if this code is related with it, it should be located into dw-mmc.c.

UHS_REG_EXT is acutally "reserved" on both the rk3288 as well as the rk=
3368.=20
rk3036/rk3128 (Cortex-A7) provide a bit description, but the tuning=20
documentation still uses the controls located in the clock controller.

So I guess UHS_REG_EXT is the real "generic" solution.

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But if you are more comfortable with it, I can also move it into th=

e

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dw_mmc- rockchip variant for the time being, until another user com=

es

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along.

I think more better that this code is located into dw_mmc-rockchip. h=

ow

about?

As described above, moving that to the rockchip part sounds sensible. A=
nd I=20
guess we can think more about it, once a second user appears.


Heiko