[PATCH v23 1/4] dt-bindings: i2c: Split AST2600 binding into a new YAML
From: Ryan Chen <ryan_chen@aspeedtech.com>
Date: 2025-11-17 02:50:52
Also in:
linux-arm-kernel, linux-devicetree, linux-i2c, lkml, openbmc
Subsystem:
arm/aspeed i2c driver, i2c subsystem host drivers, open firmware and flattened device tree bindings, the rest · Maintainers:
Ryan Chen, Andi Shyti, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
The AST2600 I2C controller introduces a completely new register map and Separate control/target register sets, unlike the mixed layout used in AST2400/AST2500. In addition, at new AST2600 configuration registers and transfer modes require new DT properties, which are incompatible with existing bindings. Therefore, this creates a dedicated binding file for AST2600 to properly describe these new hardware capabilities. A subsequent change will modify this new binding to properly describe the AST2600 hardware. The example section updated to reflect the actual AST2600 SoC register layout and interrupt configuration. Reference: aspeed-g6.dtsi (lines 885-897) -I2C bus and buffer register offsets - AST2600 I2C controller register base starts from 0x80, and the buffer region is located at 0xc00, as defined in AST2600 SOC register map. -Interrupt configuration - AST2600 I2C controller are connected to ARM GIC interrupt controller rather than the legacy internal interrupt controller. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> --- .../bindings/i2c/aspeed,ast2600-i2c.yaml | 66 +++++++++++++++++++ .../devicetree/bindings/i2c/aspeed,i2c.yaml | 3 +- 2 files changed, 67 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/i2c/aspeed,ast2600-i2c.yaml
diff --git a/Documentation/devicetree/bindings/i2c/aspeed,ast2600-i2c.yaml b/Documentation/devicetree/bindings/i2c/aspeed,ast2600-i2c.yaml
new file mode 100644
index 000000000000..c98deab6a977
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/aspeed,ast2600-i2c.yaml@@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/aspeed,ast2600-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED I2C on the AST26XX SoCs + +maintainers: + - Ryan Chen <ryan_chen@aspeedtech.com> + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + enum: + - aspeed,ast2600-i2c-bus + + reg: + items: + - description: controller registers + - description: controller buffer space + + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + description: + root clock of bus, should reference the APB + clock in the second cell + + clock-frequency: + description: Desired operating frequency of the I2C bus in Hz. + minimum: 500 + maximum: 4000000 + default: 100000 + + resets: + maxItems: 1 + +required: + - reg + - compatible + - clocks + - resets + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/aspeed-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + i2c@80 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2600-i2c-bus"; + reg = <0x80 0x80>, <0xc00 0x20>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; + clock-frequency = <100000>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + };
diff --git a/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml b/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml
index 5b9bd2feda3b..d4e4f412feba 100644
--- a/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml@@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/i2c/aspeed,i2c.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: ASPEED I2C on the AST24XX, AST25XX, and AST26XX SoCs +title: ASPEED I2C on the AST24XX, AST25XX SoCs maintainers: - Rayn Chen <rayn_chen@aspeedtech.com>
@@ -17,7 +17,6 @@ properties: enum: - aspeed,ast2400-i2c-bus - aspeed,ast2500-i2c-bus - - aspeed,ast2600-i2c-bus reg: minItems: 1
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2.34.1