Subject: Re: [PATCH v12 3/3] clk: aspeed: add AST2700 clock driver

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+static const struct clk_div_table ast2700_rgmii_div_table[] = {
+     { 0x0, 4 },
+     { 0x1, 4 },
+     { 0x2, 6 },
+     { 0x3, 8 },
+     { 0x4, 10 },
+     { 0x5, 12 },
+     { 0x6, 14 },
+     { 0x7, 16 },
+     { 0 }
+};

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+     DIVIDER_CLK(SCU1_CLK_RGMII, "rgmii", soc1_hpll,
+                 SCU1_CLK_SEL1, 25, 3, ast2700_rgmii_div_table),

Historically, aspeed has got RGMII delays wrong. Could you confirm this has
nothing to do with the 2ns delay needed by RGMII.

It is nothing to do with this delay cell.

What exactly is this clock used for? RGMII needs 2.5MHz, 25MHz and 125MHz,
which none of these dividers seems to provide.

It is RGMII clk source for MAC controller.
The clock tree is hpll-> div -> mac rgmii, and MAC controller will generate 2.5, 25,
125Mhz depend on mode. 

	Andrew