[PATCH net-next v11 2/6] dt-bindings: net: pcs: add rockchip,rk3568-xpcs support
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From: Coia Prant <hidden>
Date: 2026-10-08 17:53:13
Also in:
linux-devicetree, linux-rockchip, lkml, netdev
Subsystem:
networking drivers, open firmware and flattened device tree bindings, the rest · Maintainers:
Andrew Lunn, "David S. Miller", Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
Revision v11 of 10 in this series.
Revisions (10)
Add device tree binding documentation for the Synopsys DesignWare XPCS integrated on the Rockchip RK3568 SoC. The XPCS is accessed over the APB3 bus and internally connected to a Naneng Combo SerDes PHY. It supports 1000BASE-X, SGMII, and QSGMII modes, with four MII ports. The MII port used by the SGMII link is derived from the MAC it is routed to: GMAC0 uses port 0, GMAC1 uses port 1. The port index is not an independent board-level configuration, so the binding does not describe the ports. If a future SoC needs per-port configuration that cannot be derived, pcs-handle argument cells can be added then. The CRU reset lines (SRST_XPCS*) are intentionally not described: no in-tree user requests them, and bring-up relies on the PD_PIPE power domain, the SerDes PHY and the in-IP soft reset. They can be added later as optional without breaking ABI. Signed-off-by: Coia Prant <redacted> --- .../net/pcs/rockchip,rk3568-xpcs.yaml | 69 +++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/pcs/rockchip,rk3568-xpcs.yaml
diff --git a/Documentation/devicetree/bindings/net/pcs/rockchip,rk3568-xpcs.yaml b/Documentation/devicetree/bindings/net/pcs/rockchip,rk3568-xpcs.yaml
new file mode 100644
index 0000000000000..a331880eb11c1
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/pcs/rockchip,rk3568-xpcs.yaml@@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/pcs/rockchip,rk3568-xpcs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3568 Synopsys DesignWare Ethernet PCS + +maintainers: + - Coia Prant <coiaprant@gmail.com> + +description: | + Rockchip RK3568 SoC integrates a Synopsys DesignWare Ethernet Physical + Coding Sublayer (XPCS). + The PCS provides an interface between the Media Access Control (MAC) + and the Physical Medium Attachment (PMA) sublayer through a Media + Independent Interface (GMII). + + The XPCS is accessed over the APB3 bus and internally connected to a + Naneng Combo SerDes PHY. + It supports 1000BASE-X, SGMII and QSGMII modes. + +properties: + compatible: + const: rockchip,rk3568-xpcs + + reg: + maxItems: 1 + + clocks: + items: + - description: APB3 bus interface clock (clk_csr_i), required for register access + - description: EEE clock (clk_eee_i), required for Energy Efficient Ethernet operation + + clock-names: + items: + - const: csr + - const: eee + + phys: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - phys + - power-domains + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3568-cru.h> + #include <dt-bindings/power/rk3568-power.h> + #include <dt-bindings/phy/phy.h> + + ethernet-pcs@fda00000 { + compatible = "rockchip,rk3568-xpcs"; + reg = <0xfda00000 0x200000>; + clocks = <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>; + clock-names = "csr", "eee"; + phys = <&combphy2 PHY_TYPE_SGMII>; + power-domains = <&power RK3568_PD_PIPE>; + };
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