[PATCH v6 05/12] clk: nuvoton: ma35d1: Add missing WDT/WWDT parent clocks
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COLD26d
SUPERSEDED: 1 (1M)
From: Miquel Raynal <miquel.raynal@bootlin.com>
Date: 2026-09-30 17:26:44
Also in:
linux-clk, linux-devicetree, lkml, stable
Subsystem:
arm/nuvoton ma35 architecture, common clk framework, the rest · Maintainers:
Jacky Huang, Shan-Chun Hung, Stephen Boyd, Brian Masney, Jerome Brunet, Linus Torvalds
Status: Superseded by v10 (posted 2026-10-15). [go to v10]
Revision v6 (8 revisions archived); 1 review trailer.
Revisions (8)
The WDT and WWDT muxes list PCLK3/4096 and PCLK4/4096 among their possible parents, but the driver never registers the corresponding clocks, so these parents could never be used. Add pclk3_div4096 and pclk4_div4096 as fixed factor children of pclk3 and pclk4 and expose them through the clock provider. Reported-by: Jacky Huang <redacted> Closes: https://lore.kernel.org/linux-clk/b8a8a65b-e302-4747-bc90-4920fc48795a@gmail.com/ (local) Suggested-by: Jacky Huang <redacted> Fixes: 691521a367cf ("clk: nuvoton: Add clock driver for ma35d1 clock controller") Cc: <redacted> Link: https://lore.kernel.org/linux-clk/b8a8a65b-e302-4747-bc90-4920fc48795a@gmail.com/ (local) Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> --- drivers/clk/nuvoton/clk-ma35d1.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/nuvoton/clk-ma35d1.c b/drivers/clk/nuvoton/clk-ma35d1.c
index 6aa42a3e1be3..c914079cee2d 100644
--- a/drivers/clk/nuvoton/clk-ma35d1.c
+++ b/drivers/clk/nuvoton/clk-ma35d1.c@@ -17,7 +17,7 @@ static DEFINE_SPINLOCK(ma35d1_lock); #define PLL_MAX_NUM 5 -#define MA35D1_CLK_COUNT 236 +#define MA35D1_CLK_COUNT 238 /* Clock Control Registers Offset */ #define REG_CLK_PWRCTL 0x00
@@ -544,6 +544,8 @@ static int ma35d1_clocks_probe(struct platform_device *pdev) hws[HCLK3] = ma35d1_clk_fixed_factor(dev, "hclk3", "sysclk1_mux", 1, 2); hws[PCLK3] = ma35d1_clk_fixed_factor(dev, "pclk3", "sysclk1_mux", 1, 2); hws[PCLK4] = ma35d1_clk_fixed_factor(dev, "pclk4", "sysclk1_mux", 1, 2); + hws[PCLK3_DIV4096] = ma35d1_clk_fixed_factor(dev, "pclk3_div4096", "pclk3", 1, 4096); + hws[PCLK4_DIV4096] = ma35d1_clk_fixed_factor(dev, "pclk4_div4096", "pclk4", 1, 4096); hws[USBPHY0] = ma35d1_clk_fixed("usbphy0", 480000000); hws[USBPHY1] = ma35d1_clk_fixed("usbphy1", 480000000);
--
2.55.0