Some SoCs have a limited number of IOMMU Stream IDs (SIDs) and
hardware that inherently shares them. For example, the NXP i.MX95
only has 64 SIDs, only 6 bits for SID in the system chip bus.
However there are many device IPs, such as SDHC, PCIE, NETC, GPU,
NPU, Display, VPU, ISP, ISI, JPEG, SATA, DMA and etc. Each Kind IP has
mutilple instances inside the SoC. So I introudce this patchset to
support shared SID.
The current ARM SMMUv3 driver rejects this with:
"Aliasing StreamID unsupported, expect DMA to be broken"
I took comments in [1] and implement this patchset and only want to
support a very simple case that multiple platform devices share one SID.
[1] https://lore.kernel.org/linux-iommu/DU0PR04MB94172CB3F138AD39E9B6DEEF887F9@DU0PR04MB9417.eurprd04.prod.outlook.com/ (local)
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
Changes in v3:
- Drop the conversion to use xarray
- Only SID-sharing for single SID device
- Follow Nicolin's suggestion https://lore.kernel.org/linux-iommu/arG6hmng3NddGEHm@nvidia.com/ (local)
- Link to v2: https://lore.kernel.org/linux-iommu/20260921-smmu-shared-sid-v2-0-4b656ce68178@nxp.com/ (local)
Changes in v2:
- Only update cover-letter to make it clear about why introducing shared
SID
- Link to v1: https://patch.msgid.link/20260916-smmu-shared-sid-v1-0-517384504aee@nxp.com
---
Peng Fan (3):
iommu/arm-smmu-v3: Support shared SIDs in insert/remove_master
iommu/arm-smmu-v3: Group aliasing devices into the same IOMMU group
iommu/arm-smmu-v3: Wire up shared-SID STE ordering and feature gating
.../iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 2 +-
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 3 +
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 153 +++++++++++++++++----
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 9 ++
4 files changed, 137 insertions(+), 30 deletions(-)
---
base-commit: 86fb14622b7ccaac8916e5541bebc4d70f64331b
change-id: 20260916-smmu-shared-sid-e488f6c4d4f0
Best regards,
--
Peng Fan [off-list ref]