[PATCH RFC 00/10] ARM: Add support for Cortina Systems CS75xx and Securifi Almond+
From: Fil Dunsky via B4 Relay <devnull+filipp.dunsky.gmail.com@kernel.org>
Date: 2026-09-30 07:00:02
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This series adds initial support for the Cortina Systems CS75xx
("Goldengate G2") network processors and the first board using one, the
Securifi Almond+ touchscreen Wi-Fi router (CS7542, 2x Cortex-A9 r2p1,
PL310 r3p2, 512 MiB DDR3, 512 MiB NAND).
There is no public documentation for the SoC. The register information
comes from the GPL vendor kernels (Linux 2.6.36 for the Almond+, Linux
4.9 for the Verizon FiOS G1100 which uses the same SoC) and from
disassembly of the stock U-Boot 2009.11. A full out-of-tree port
(clock, irqchip, GPIO, I2C, RTC, NAND, PCIe, MDIO and the packet engine)
runs on Linux 6.18 in OpenWrt; this series is the first, minimal step to
get the platform into mainline:
- bindings: vendor prefix, SoC/board compatibles, an SMP enable method
and the UART,
- the platform Kconfig and SMP bring-up (the generic DT machine is
used, there is no DT_MACHINE_START),
- DEBUG_LL for UART0,
- a UART driver with console and earlycon support,
- SoC dtsi and board dts describing the CPUs, GIC, SCU, timers, L2,
UARTs and memory,
- multi_v7_defconfig and MAINTAINERS updates.
Patches 6-7 (serial binding and driver) do not depend on the rest and
can go through the tty tree.
Testing: build tested with multi_v7_defconfig (GCC 14 and Clang 21,
W=1) and checked with dt_binding_check/dtbs_check. On a Securifi
Almond+ this series boots next-20260929 to an initramfs shell with
both CPUs online ("smp: Brought up 1 node, 2 CPUs"; IPIs and the TWD
timer tick on both cores); the L2C-310, the global and TWD timers and
the UART driver (ttyCS0) come up. The kernel was started from a
running OpenWrt system with a small kexec-style loader rather than
from the stock U-Boot, because U-Boot enters the kernel with the MMU
on (see 2 below).
Things I would like feedback on, hence the RFC:
1. The stock U-Boot arms the CPU0 private (TWD) watchdog before
starting the kernel; without a driver the board resets after ~300
seconds. The OpenWrt port disarms it in init_early, which I did not
want to propose here. Instead, a driver for "arm,cortex-a9-twd-wdt"
(the binding exists, but there is currently no driver for it) that
takes over the running watchdog on all CPUs is written and tested
on this board; I will post it with the follow-up series. Until
then, this series on its own boots but resets after ~5 minutes.
Is a TWD watchdog driver the preferred way to deal with this?
2. The same U-Boot enters the kernel with the MMU and data cache
enabled (identity map with XN set, dirty lines left in the D-cache),
which breaks the decompressor. The OpenWrt port carries a small
workaround at the start of arch/arm/boot/compressed/head.S that
cleans the cache and turns the MMU off. It is not part of this series.
Replacing the bootloader is possible but risky for users of this
(discontinued) device. Would a quirk of that kind be acceptable in
head.S at all, or should this be solved outside the kernel (e.g. a
chain-loaded bootloader)? For the tests below the kernel was started
from a running Linux with the MMU off, so this was not an issue.
3. The APB clock is 100, 150 or 170 MHz depending on the boot strap pins.
It is modelled as a fixed-clock with the rate set in the board dts.
A clock driver for the global control block, which also contains the
strap, pinmux and reset registers, will follow and replace it.
4. The Cortex-A9 r2p1 is also affected by errata 742230, 742231, 743622
and 751472, whose workarounds are not available on multiplatform
kernels because they are expected to be applied by the bootloader.
The stock U-Boot does not apply them. Is there a preferred way to
deal with this?
5. The UART ports are named ttyCS to avoid clashing with the 8250 driver
in multi_v7_defconfig, and PORT_GENERIC is used instead of a new port
type. The FIFO depth is not documented; the driver assumes 16.
6. The top 64 MiB of RAM are reserved: the vendor firmware gives them to
the packet engine queue manager and the stock kernel is booted with
mem=448M. The reservation will be referenced by the network driver
later; I kept it now so that the memory is not handed out and later
claimed.
Planned follow-ups, as separate series: the regbus interrupt
controller, GPIO, I2C and TWD watchdog (ready, tested on this board),
then the global control block/clock, RTC, NAND,
PCIe (DesignWare glue), MDIO, the Ethernet/packet engine and a fix for
the SX8650 touchscreen.
---
Fil Dunsky (10):
dt-bindings: vendor-prefixes: Add Securifi
dt-bindings: arm: Add Cortina Systems CS7542 and Securifi Almond+
dt-bindings: arm: cpus: Add Cortina Systems CS7542 enable method
ARM: cortina: Add support for the CS75xx SoC family
ARM: debug: Add Cortina Systems CS75xx UART0 support
dt-bindings: serial: Add Cortina Systems CS7542 UART
tty: serial: Add Cortina Systems CS75xx UART driver
ARM: dts: cortina: Add CS7542 SoC and Securifi Almond+ board
ARM: multi_v7_defconfig: Enable Cortina Systems CS75xx support
MAINTAINERS: Add entry for Cortina Systems CS75xx
Documentation/devicetree/bindings/arm/cortina.yaml | 31 ++
Documentation/devicetree/bindings/arm/cpus.yaml | 2 +
.../bindings/serial/cortina,cs7542-uart.yaml | 50 ++
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
MAINTAINERS | 11 +
arch/arm/Kconfig | 2 +
arch/arm/Kconfig.debug | 16 +-
arch/arm/Makefile | 1 +
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/cortina/Makefile | 3 +
.../dts/cortina/cs7542-securifi-almondplus.dts | 55 +++
arch/arm/boot/dts/cortina/cs7542.dtsi | 127 +++++
arch/arm/configs/multi_v7_defconfig | 3 +
arch/arm/include/debug/cs75xx.S | 36 ++
arch/arm/mach-cortina/Kconfig | 18 +
arch/arm/mach-cortina/Makefile | 2 +
arch/arm/mach-cortina/platsmp.c | 71 +++
drivers/tty/serial/Kconfig | 24 +
drivers/tty/serial/Makefile | 1 +
drivers/tty/serial/cs75xx-uart.c | 546 +++++++++++++++++++++
20 files changed, 1000 insertions(+), 2 deletions(-)
---
base-commit: 6474fa070f2b8013b4b87350b775b8c3be6e8aac
change-id: 20260930-b4-cs75xx-033a2c047508
Best regards,
--
Fil Dunsky [off-list ref]