[PATCH v2 03/14] perf cs-etm: Break branch history when instruction memory is unavailable
From: Leo Yan <leo.yan@arm.com>
Date: 2026-09-23 15:22:17
Also in:
linux-perf-users, lkml
Subsystem:
arm/coresight framework and drivers, performance events subsystem, performance events tooling arm64, the rest · Maintainers:
Suzuki K Poulose, Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Namhyung Kim, Linus Torvalds
The decoder currently ignores OCSD_GEN_TRC_ELEM_ADDR_NACC, allowing a subsequent range to be paired with stale branch history from before the unreadable code. Treat an inaccessible instruction address as a discontinuity and flush the pending range and branch history before processing subsequent elements. Assisted-by: Codex:gpt-6 Signed-off-by: Leo Yan <leo.yan@arm.com> --- tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
index 26940f1f1b0bf44c8671d80020597c672c361c1a..35ca1a23e12735416d0d412a949595efc5bfe50a 100644
--- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
+++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c@@ -594,7 +594,8 @@ static ocsd_datapath_resp_t cs_etm_decoder__gen_trace_elem_printer( if (type == OCSD_GEN_TRC_ELEM_EO_TRACE || type == OCSD_GEN_TRC_ELEM_NO_SYNC || - type == OCSD_GEN_TRC_ELEM_TRACE_ON) + type == OCSD_GEN_TRC_ELEM_TRACE_ON || + type == OCSD_GEN_TRC_ELEM_ADDR_NACC) resp = cs_etm_decoder__buffer_discontinuity(etmq, packet_queue, trace_chan_id); else if (type == OCSD_GEN_TRC_ELEM_INSTR_RANGE)
--
2.34.1