[PATCH v2 1/8] dt-bindings: clock: rk3588: add PCLK_DDR_MON_CH clocks
flat view
COOLING10d
From: Sebastian Reichel <hidden>
Date: 2026-09-21 20:33:34
Also in:
linux-clk, linux-devicetree, linux-pm, linux-rockchip, lkml
Subsystem:
common clk framework, open firmware and flattened device tree bindings, the rest · Maintainers:
Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
Revision v2 of 2 in this series.
Revisions (2)
- v1 [diff vs current]
- v2 current
From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> On RK3588, each memory channel has its own DDR bandwidth monitor silicon, and each instance of that has its own clock gate that drives the monitor logic. Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Signed-off-by: Sebastian Reichel <redacted> --- include/dt-bindings/clock/rockchip,rk3588-cru.h | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/include/dt-bindings/clock/rockchip,rk3588-cru.h b/include/dt-bindings/clock/rockchip,rk3588-cru.h
index 7528034cff56..6ea25019ebb4 100644
--- a/include/dt-bindings/clock/rockchip,rk3588-cru.h
+++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h@@ -738,6 +738,10 @@ #define I2S1_8CH_MCLKOUT_TO_IO 723 #define I2S2_2CH_MCLKOUT_TO_IO 724 #define I2S3_2CH_MCLKOUT_TO_IO 725 +#define PCLK_DDR_MON_CH0 726 +#define PCLK_DDR_MON_CH1 727 +#define PCLK_DDR_MON_CH2 728 +#define PCLK_DDR_MON_CH3 729 /* scmi-clocks indices */
--
2.53.0