[PATCH v9 3/3] PCI: dwc: Remove redundant MPS configuration
From: Hans Zhang <18255117159@163.com>
Date: 2026-09-16 15:40:06
Also in:
linux-amlogic, linux-pci, linux-rockchip, lkml
Subsystem:
pci native host bridge and endpoint drivers, pci subsystem, pcie driver for amlogic meson, the rest · Maintainers:
Lorenzo Pieralisi, Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas, Yue Wang, Linus Torvalds
The Meson PCIe controller driver manually configures maximum payload size (MPS) through meson_set_max_payload, duplicating functionality now centralized in the PCI core. Deprecating redundant code simplifies the driver and aligns it with the consolidated MPS management strategy, improving long-term maintainability. With meson_set_max_payload() gone, meson_size_to_payload() is only used for MRRS. Rename it to meson_size_to_mrrs(), update the warning message, and drop the now-unused PCIE_CAP_MAX_PAYLOAD_SIZE and MAX_PAYLOAD_SIZE macros. Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pci-meson.c | 25 +++---------------------- 1 file changed, 3 insertions(+), 22 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c
index 8559d132dcde..1d3687566dda 100644
--- a/drivers/pci/controller/dwc/pci-meson.c
+++ b/drivers/pci/controller/dwc/pci-meson.c@@ -21,7 +21,6 @@ #define to_meson_pcie(x) dev_get_drvdata((x)->dev) -#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5) #define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12) /* PCIe specific config registers */
@@ -37,7 +36,6 @@ #define PM_CURRENT_STATE(x) (((x) >> 7) & 0x1) #define PORT_CLK_RATE 100000000UL -#define MAX_PAYLOAD_SIZE 256 #define MAX_READ_REQ_SIZE 256 #define PCIE_RESET_DELAY 500 #define PCIE_SHARED_RESET 1
@@ -256,7 +254,7 @@ static void meson_pcie_ltssm_enable(struct meson_pcie *mp) meson_cfg_writel(mp, val, PCIE_CFG0); } -static int meson_size_to_payload(struct meson_pcie *mp, int size) +static int meson_size_to_mrrs(struct meson_pcie *mp, int size) { struct device *dev = mp->pci.dev;
@@ -266,35 +264,19 @@ static int meson_size_to_payload(struct meson_pcie *mp, int size) * than 2^12, just set to default size 2^(1+7). */ if (!is_power_of_2(size) || size < 128 || size > 4096) { - dev_warn(dev, "payload size %d, set to default 256\n", size); + dev_warn(dev, "MRRS %d, set to default 256\n", size); return 1; } return fls(size) - 8; } -static void meson_set_max_payload(struct meson_pcie *mp, int size) -{ - struct dw_pcie *pci = &mp->pci; - u32 val; - u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - int max_payload_size = meson_size_to_payload(mp, size); - - val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); - val &= ~PCI_EXP_DEVCTL_PAYLOAD; - dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val); - - val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); - val |= PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size); - dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val); -} - static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size) { struct dw_pcie *pci = &mp->pci; u32 val; u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - int max_rd_req_size = meson_size_to_payload(mp, size); + int max_rd_req_size = meson_size_to_mrrs(mp, size); val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); val &= ~PCI_EXP_DEVCTL_READRQ;
@@ -363,7 +345,6 @@ static int meson_pcie_host_init(struct dw_pcie_rp *pp) pp->bridge->ops = &meson_pci_ops; - meson_set_max_payload(mp, MAX_PAYLOAD_SIZE); meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE); return 0;
--
2.34.1