[PATCH v5 7/7] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on ROCK 5 ITX
From: Ricardo Pardini via B4 Relay <devnull+ricardo.pardini.net@kernel.org>
Date: 2026-09-10 20:08:06
Also in:
b4-sent, linux-devicetree, linux-rockchip, lkml, netdev
Subsystem:
the rest · Maintainer:
Linus Torvalds
From: Ricardo Pardini <redacted> The Radxa ROCK 5 ITX carries two on-board Realtek RTL8125 NICs behind pcie2x1l1 and pcie2x1l2. Describe the fixed function nodes and attach ethernet0/ethernet1 aliases, so that U-Boot's fdt_fixup_ethernet() can inject mac-address properties from its ethaddr/eth1addr env, for stable MACs across boots that both U-Boot and the kernel agree on. Signed-off-by: Ricardo Pardini <redacted> --- arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
index 6f25e088f3189..f1d6647c57bf9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts@@ -20,6 +20,8 @@ / { compatible = "radxa,rock-5-itx", "rockchip,rk3588"; aliases { + ethernet0 = &rtl_eth0; + ethernet1 = &rtl_eth1; mmc0 = &sdhci; mmc1 = &sdmmc; mmc2 = &sdio;
@@ -631,6 +633,20 @@ &pcie2x1l1 { reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_lan>; status = "okay"; + + pcie@0,0 { + reg = <0x300000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + device_type = "pci"; + bus-range = <0x30 0x3f>; + + rtl_eth0: ethernet@0,0 { + compatible = "pci10ec,8125"; + reg = <0x310000 0 0 0 0>; + }; + }; }; /* RTL8125B_2 */
@@ -640,6 +656,20 @@ &pcie2x1l2 { reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_lan_phy2>; status = "okay"; + + pcie@0,0 { + reg = <0x400000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + device_type = "pci"; + bus-range = <0x40 0x4f>; + + rtl_eth1: ethernet@0,0 { + compatible = "pci10ec,8125"; + reg = <0x410000 0 0 0 0>; + }; + }; }; &pcie30phy {
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2.55.0