[PATCH 1/2] clk: imx: fracn-gppll: Add 350 MHz support
From: Frieder Schrempf <hidden>
Date: 2026-09-10 15:20:22
Also in:
imx, linux-clk, linux-devicetree, lkml
Subsystem:
common clk framework, nxp i.mx clock drivers, the rest · Maintainers:
Stephen Boyd, Brian Masney, Jerome Brunet, Abel Vesa, Linus Torvalds
From: Mikhail Vaniulin <redacted> Add the 350 MHz frequency support that can be used for display with pixelclk of 50 MHz. The divider of 7 is important for LVDS output on i.MX93. It is also usable for parallel output. Signed-off-by: Mikhail Vaniulin <redacted> Signed-off-by: Frieder Schrempf <redacted> --- drivers/clk/imx/clk-fracn-gppll.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c
index 4048c16c0578..4d83907553c4 100644
--- a/drivers/clk/imx/clk-fracn-gppll.c
+++ b/drivers/clk/imx/clk-fracn-gppll.c@@ -89,6 +89,7 @@ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = { PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9), PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12), PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10), + PLL_FRACN_GP(350000000U, 175, 0, 1, 0, 12), PLL_FRACN_GP(333333333U, 125, 0, 1, 1, 9), PLL_FRACN_GP(332600000U, 138, 584, 1000, 0, 10), PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12),
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2.55.0