[PATCH net-next v6 13/14] misc: lan966x-pci: dts: extend cpu reg to cover PCIE DBI space
flat view
COLD24d
REVIEWED: 14 (14M)
From: Daniel Machon <daniel.machon@microchip.com>
Date: 2026-09-09 13:01:18
Also in:
bpf, lkml, netdev
Subsystem:
char and misc drivers, microchip lan966x pci driver, the rest · Maintainers:
Arnd Bergmann, Greg Kroah-Hartman, Herve Codina, Linus Torvalds
1 review trailer (1 from subsystem maintainers).
The ATU outbound windows used by the FDMA engine are programmed through registers at offset 0x400000+, which falls outside the current cpu reg mapping. Extend the cpu reg size from 0x100000 (1MB) to 0x800000 (8MB) to cover the full PCIE DBI and iATU register space. Tested-by: Herve Codina <herve.codina@bootlin.com> Signed-off-by: Daniel Machon <daniel.machon@microchip.com> --- drivers/misc/lan966x_pci.dtso | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/misc/lan966x_pci.dtso b/drivers/misc/lan966x_pci.dtso
index 7b196b0a0eb6..7bb726550caf 100644
--- a/drivers/misc/lan966x_pci.dtso
+++ b/drivers/misc/lan966x_pci.dtso@@ -135,7 +135,7 @@ lan966x_phy1: ethernet-lan966x_phy@2 { switch: switch@e0000000 { compatible = "microchip,lan966x-switch"; - reg = <0xe0000000 0x0100000>, + reg = <0xe0000000 0x0800000>, <0xe2000000 0x0800000>; reg-names = "cpu", "gcb";
--
2.34.1