On Tue, Sep 08 2026 at 20:15, Pranjal Shrivastava wrote:
On Tue, Sep 08, 2026 at 09:40:49PM +0200, Thomas Gleixner wrote:
quoted
So this all can be solved at the device domain level without sprinkling
per interrupt invocations including conditionals all over the place.
Ack. I was wondering if the irq core should also cache the message for
platform MSIs like it's done for PCI ? Would that be a bad idea? Or is
it this way by design? (I'm having to cache the msg in the iommu driver
atm).
Sure. This can be done in irq_chip_write_msi_msg() before invoking the
chip callback. That makes the PCI caching redundant, but it can't be
removed because of other historical layering violations in that
context. So adding it to the core requires to add a comment why this has
to stay in the PCI write function.