Re: [PATCH v5 00/15] Add initial support for Qualcomm Kuno SoC

On 8/27/2026 11:21 PM, Hardeep Sharma wrote:

This series adds initial support for the Qualcomm Kuno SoC and the Kuno
IDP reference board.

Kuno is a 32-bit ARM (Cortex-A7) Qualcomm platform. This series brings up
the essential SoC infrastructure required to boot to a serial console:

   - Global Clock Controller (GCC) and RPMh clock controller
   - RPMh power domains
   - Interconnect (NoC) provider
   - TLMM pin controller
   - PDC interrupt controller and SCM firmware interface
   - Devicetree for the SoC and the Kuno IDP board

The soc: qcom: geni-se patch allows the GENI serial engine driver to be
selected on 32-bit ARM Qualcomm SoCs, which the debug UART console
depends on.

Signed-off-by: Hardeep Sharma <redacted>
---
Changes in v5:
- Selected QCOM_GDSC from the Kuno GCC config. The driver registers GDSCs
   (added in v4), so like the other Qualcomm GCC drivers it must select
   QCOM_GDSC; otherwise, in a configuration where nothing else enables it
   (e.g. COMPILE_TEST or a minimal Kuno-only build), gdsc_register() returns
   -ENOSYS and the clock controller fails to probe.
- Link to v4: https://lore.kernel.org/all/20260827-kuno-soc-support-v4-0-dd34f235fc1a@oss.qualcomm.com/ (local)

Changes in v4:
- Addressed v3 review feedback:
   - Registered the interconnect NoC provider from an explicit
     core_initcall() instead of module_platform_driver(), matching the
     established qcom interconnect driver convention.
   - Replaced the NA mux-slot placeholder with _ across the pinctrl
     PINGROUP table, matching the upstream qcom pinctrl convention.
   - Added minItems: 1 to the interconnect binding clocks property so a
     single clock is valid (system-noc), and aligned the binding
     examples with the sdx75 labelled-node style.
   - Added GDSC power-domain support to the Kuno GCC: the binding now
     defines GDSC macros and the driver registers the EMAC0, PCIe and
     USB20 GDSCs, so #power-domain-cells has real backing providers.
   - Split the cpu-idle-states phandle list so each phandle is on its
     own line.
   - Collected Acked-by / Reviewed-by tags from v3.
- Link to v3: https://lore.kernel.org/all/20260821-kuno-soc-support-v3-0-196e2b306368@oss.qualcomm.com/ (local)

Changes in v3:
- Addressed v2 review feedback:
   - Reworked the interconnect binding clocks: dropped clock-names and
     replaced the flexible min/maxItems list with fixed per-compatible
     clocks (aggre-noc: 2, system-noc: 1), required where present and
     disallowed otherwise, matching the sdx75/glymur shape.
   - Made #power-domain-cells required on the Kuno GCC binding and
     declared it on the SoC gcc node, since the Kuno GCC hosts GDSCs and
     is a power-domain provider (following qcom,sdx75-gcc); the driver's
     GDSC support will follow separately.
   - Made the GPIO65/66 QDSS CTI trig1 funcsel-3 route selectable: added
     a distinct qdss_cti_trig1_mire pin function (and allowed it in the
     TLMM binding enum), as the duplicate funcsel-2/3 entry left
     funcsel-3 unreachable.
   - Collected Acked-by / Reviewed-by tags from v2.
- Link to v2: https://lore.kernel.org/all/20260814-kuno-soc-support-v2-0-3079794f0f73@oss.qualcomm.com/ (local)

Changes in v2:
- Addressed v1 review feedback:
   - Reworked soc: qcom: geni-se commit message; dropped the Fixes: tag.
   - Reworded dt-bindings commit messages to the "Document X for the
     Qualcomm Kuno SoC" one-liner form.
   - Canonicalized copyright headers on interconnect binding / driver /
     NoC ID header to the single-line Qualcomm Technologies form.
   - Dropped unused <linux/mod_devicetable.h> from the interconnect
     driver.
   - Fixed MODULE_DESCRIPTION casing "KUNO" -> "Kuno" in the interconnect
     driver.
   - Extended interconnect binding to optionally allow up to four QoS AHB
     clocks (matches sdx75/glymur shape).
   - Cleaned up brace/space style in gcc-kuno.c to match peer clock
     drivers.
   - Reworked initial DTS: moved idle-states / domain-idle-states inside
     cpus{}, wrapped fixed clocks in a clocks{} container with peer node
     names (xo-board, sleep-clk), dropped the pcie_pipe_clk fixed-clock
     stub (the GCC 4th clock now uses <0> in DTS to match the sdx75
     idiom; the YAML example uses a named placeholder), dropped the
     RPMHPD_CX power-domain reference on GCC (Kuno GCC has no GDSCs /
     no corner votes / no pm_runtime, so the reference was inert), and
     added a bootloader hand-off comment on the memory node.
   - Collected Acked-by / Reviewed-by tags from v1.
- Link to v1: https://lore.kernel.org/all/20260809-kuno-soc-support-v1-0-5e0ede4a0c72@oss.qualcomm.com/ (local)

---
Hardeep Sharma (15):
       soc: qcom: geni-se: allow selection on 32-bit ARM Qualcomm SoCs
       dt-bindings: power: rpmpd: Document Kuno RPMh power domains
       pmdomain: qcom: rpmhpd: Add power domains for Kuno
       dt-bindings: clock: qcom,rpmhcc: Add Kuno RPMh clock controller
       clk: qcom: clk-rpmh: Add support for Kuno RPMh clocks
       dt-bindings: interconnect: Add Qualcomm Kuno NoC
       interconnect: qcom: Add Kuno interconnect provider driver
       dt-bindings: pinctrl: qcom: Add Kuno TLMM
       pinctrl: qcom: Add Kuno pinctrl driver
       dt-bindings: clock: qcom: Add Kuno Global Clock Controller
       clk: qcom: Add Global Clock Controller driver for Kuno
       dt-bindings: interrupt-controller: qcom,pdc: Add Kuno compatible string
       dt-bindings: firmware: qcom,scm: Document SCM on Kuno SoC
       dt-bindings: arm: qcom: Document Kuno IDP board
       ARM: dts: qcom: Add initial device tree for Kuno SoC

  .../devicetree/bindings/arm/qcom-soc.yaml          |    4 +-
  Documentation/devicetree/bindings/arm/qcom.yaml    |    5 +
  .../devicetree/bindings/clock/qcom,kuno-gcc.yaml   |   52 +
  .../devicetree/bindings/clock/qcom,rpmhcc.yaml     |    1 +
  .../devicetree/bindings/firmware/qcom,scm.yaml     |    1 +
  .../bindings/interconnect/qcom,kuno-rpmh.yaml      |  118 ++
  .../bindings/interrupt-controller/qcom,pdc.yaml    |    1 +
  .../bindings/pinctrl/qcom,kuno-tlmm.yaml           |  110 ++
  .../devicetree/bindings/power/qcom,rpmpd.yaml      |    1 +
  arch/arm/boot/dts/qcom/Makefile                    |    1 +
  arch/arm/boot/dts/qcom/qcom-kuno-idp.dts           |   25 +
  arch/arm/boot/dts/qcom/qcom-kuno.dtsi              |  423 ++++++
  drivers/clk/qcom/Kconfig                           |   11 +
  drivers/clk/qcom/Makefile                          |    1 +
  drivers/clk/qcom/clk-rpmh.c                        |   15 +
  drivers/clk/qcom/gcc-kuno.c                        | 1483 ++++++++++++++++++++
  drivers/interconnect/qcom/Kconfig                  |   13 +
  drivers/interconnect/qcom/Makefile                 |    2 +
  drivers/interconnect/qcom/kuno.c                   |  988 +++++++++++++
  drivers/pinctrl/qcom/Kconfig.msm                   |   11 +
  drivers/pinctrl/qcom/Makefile                      |    1 +
  drivers/pinctrl/qcom/pinctrl-kuno.c                |  801 +++++++++++
  drivers/pmdomain/qcom/rpmhpd.c                     |   16 +
  drivers/soc/qcom/Kconfig                           |    1 -
  include/dt-bindings/clock/qcom,kuno-gcc.h          |  100 ++
  include/dt-bindings/interconnect/qcom,kuno.h       |   89 ++
  26 files changed, 4271 insertions(+), 3 deletions(-)
---
base-commit: f82a5da2f04960df9fb57489992d03dd5e64ec6f
change-id: 20260809-kuno-soc-support-1dab826de0bf

Best regards,
--
Hardeep Sharma [off-list ref]

Hello All,

Several patches from the series have already been picked up and applied
through their respective subsystem trees.

The remaining patches listed below are ready to be picked up as well:

  [PATCH v5 06/15] dt-bindings: interconnect: Add Qualcomm Kuno NoC
  [PATCH v5 07/15] interconnect: qcom: Add Kuno interconnect provider driver
  [PATCH v5 14/15] dt-bindings: arm: qcom: Document Kuno IDP board

Since the majority of the series has already been applied, I would
appreciate it if the remaining patches could also be considered for
inclusion.

Please let me know if there are any outstanding concerns or additional
changes required from my side.

Thank you for your time and review.

Best Wishes,
Hardeep Sharma