[PATCH] arm64: dts: renesas: r8a779g0: Add MSI cells to GICv3 ITS
From: Marek Vasut <marek.vasut+renesas@mailbox.org>
Date: 2026-09-08 16:23:47
Also in:
linux-devicetree, linux-renesas-soc, lkml
Subsystem:
arm/risc-v/renesas architecture, the rest · Maintainers:
Geert Uytterhoeven, Magnus Damm, Linus Torvalds
Fill in missing #msi-cells = <1> into the GIC ITS node, update
its-parent phandles and fill in 1:1 msi-map .
Fixes: 7fe73a3a3f2c ("arm64: dts: renesas: r8a779g0: Add GICv3 ITS and update PCIe nodes")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
---
arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
index ea6495261c2bb..ca17bfbf83fdf 100644
--- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi@@ -809,7 +809,8 @@ pciec0: pcie@e65d0000 { resets = <&cpg 624>; reset-names = "pwr"; max-link-speed = <4>; - msi-parent = <&its>; + msi-parent = <&its 0>; + msi-map = <0x0 &its 0x0 0x10000>; num-lanes = <2>; #address-cells = <3>; #size-cells = <2>;
@@ -857,7 +858,8 @@ pciec1: pcie@e65d8000 { resets = <&cpg 625>; reset-names = "pwr"; max-link-speed = <4>; - msi-parent = <&its>; + msi-parent = <&its 0>; + msi-map = <0x0 &its 0x0 0x10000>; num-lanes = <2>; #address-cells = <3>; #size-cells = <2>;
@@ -2165,6 +2167,7 @@ its: msi-controller@40000 { reg = <0x0 0x40000 0x0 0x20000>; dma-noncoherent; msi-controller; + #msi-cells = <1>; }; };
--
2.53.0