Re: [PATCH v20 05/14] KVM: arm64: Set PSTATE.EXLOCK when entering an exception
From: "Lorenzo Stoakes (ARM)" <ljs@kernel.org>
Date: 2026-09-04 13:04:37
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On Tue, Sep 01, 2026 at 10:47:03PM +0100, Mark Brown wrote:
As per DDI 0487 R_WTXBY we need to manage PSTATE.EXLOCK when entering an
I'm guessing this is the doc at this unreasonably huge URI? :) https://support.arm.com/documentation/ddi0487/mc/-Part-D-The-AArch64-System-Level-Architecture/-Chapter-D1-The-AArch64-System-Level-Programmers--Model/-D1-4-Exceptions/-D1-4-2-Exception-entry?lang=en#wtxby
exception, when the exception is entered from a lower EL the bit is cleared while if entering from the same EL it is set to GCSCR_ELx.EXLOCKEN. Implement this behaviour in enter_exception64().
Ack, all makes sense and matches the doc.
Reviewed-by: Yuan Yao <redacted> Signed-off-by: Mark Brown <broonie@kernel.org>
All LGTM! A couple small nits but otherwise: Reviewed-by: Lorenzo Stoakes (ARM) <ljs@kernel.org>
quoted hunk ↗ jump to hunk
--- arch/arm64/include/uapi/asm/ptrace.h | 1 + arch/arm64/kvm/hyp/exception.c | 37 ++++++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+)diff --git a/arch/arm64/include/uapi/asm/ptrace.h b/arch/arm64/include/uapi/asm/ptrace.h index 15649a253a57..eed7f1226be6 100644 --- a/arch/arm64/include/uapi/asm/ptrace.h +++ b/arch/arm64/include/uapi/asm/ptrace.h@@ -56,6 +56,7 @@ #define PSR_C_BIT 0x20000000 #define PSR_Z_BIT 0x40000000 #define PSR_N_BIT 0x80000000 +#define PSR_EXLOCK_BIT 0x400000000
Ah yeah I see this matches BIT_ULL(34) /* PSTATE.EXLOCK */ in emulate-nested.c (which you later replace with this :)
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#define PSR_BTYPE_SHIFT 10diff --git a/arch/arm64/kvm/hyp/exception.c b/arch/arm64/kvm/hyp/exception.c index 754e2dc1df54..85c873644fe9 100644 --- a/arch/arm64/kvm/hyp/exception.c +++ b/arch/arm64/kvm/hyp/exception.c@@ -49,6 +49,38 @@ static void __vcpu_write_spsr_und(struct kvm_vcpu *vcpu, u64 val) vcpu->arch.ctxt.spsr_und = val; } +static unsigned long compute_exlock(struct kvm_vcpu *vcpu, + unsigned long mode, + unsigned long target_mode) +{ + u64 gcscr; + + if (!kvm_has_gcs(kern_hyp_va(vcpu->kvm))) + return 0; + + /* GCS can't be enabled for 32 bit */ + if (mode & PSR_MODE32_BIT) + return 0;
Ack makes sense.
+ + /* When taking an exception to a higher EL EXLOCK is cleared. */ + if ((mode | PSR_MODE_THREAD_BIT) != target_mode) + return 0;
Ack makes sense as per doc.
+ + /* + * When taking an exception to the same EL EXLOCK is set to + * the effective value of GCSR_ELx.EXLOCKEN.
NIT: Typo? Other references to this here are for GCSCR_ELx.EXLOCKEN.
+ */ + if (is_hyp_ctxt(vcpu)) + gcscr = vcpu_read_sys_reg(vcpu, GCSCR_EL2);
I guess with VHE this does the automagically 'think it's in EL2' even if it's nested in EL1 stuff? :)
+ else + gcscr = vcpu_read_sys_reg(vcpu, GCSCR_EL1); + + if (gcscr & GCSCR_ELx_EXLOCKEN) + return PSR_EXLOCK_BIT;
This all LGTM.
quoted hunk ↗ jump to hunk
+ + return 0; +} + /* * This performs the exception entry at a given EL (@target_mode), stashing PC * and PSTATE into ELR and SPSR respectively, and compute the new PC/PSTATE.@@ -138,6 +170,11 @@ static void enter_exception64(struct kvm_vcpu *vcpu, unsigned long target_mode, // PSTATE.BTYPE is set to zero upon any exception to AArch64 // See ARM DDI 0487E.a, pages D1-2293 to D1-2294. + // PSTATE.EXLOCK is set to 0 upon any exception to a higher + // EL, or to GCSCR_ELx.EXLOCKEN for an exception to the same + // exception level. See ARM DDI 0487 R_WTXBY.
Yeah confirmed: "If FEAT_GCS is implemented, PSTATE.EXLOCK is updated based on the following situations: On taking an exception to the same Exception level, PSTATE.EXLOCK is set to the Effective value of GCSCR_ELx.EXLOCKEN for the current Exception level. On taking an exception to a higher Exception level, PSTATE.EXLOCK is set to 0." A slight nit is that maybe the comment should live with compute_exlock() but it's no big deal.
+ new |= compute_exlock(vcpu, mode, target_mode); + new |= PSR_D_BIT; new |= PSR_A_BIT; new |= PSR_I_BIT; -- 2.47.3
-- Cheers, Lorenzo