[PATCH v48 7/7] arm64: dts: imx8ulp: add reserved memory for EdgeLock Enclave
From: <hidden>
Date: 2026-09-04 09:22:47
Also in:
imx, linux-devicetree, linux-doc, lkml
Subsystem:
arm/freescale imx / mxc / layerscape arm architecture, the rest · Maintainers:
Frank Li, Sascha Hauer, Linus Torvalds
From: Pankaj Gupta <pankaj.gupta@nxp.com> Reserve 1MB of DDR for the EdgeLock Enclave. The enclave hardware can only access DDR in the 0x80000000 - 0xafffffff window, so constrain the pool to that range with alloc-ranges and let the kernel choose the placement rather than hardcoding an address. Provide this as a shared imx8ulp-firmware.dtsi that also enables the hsm0 node and wires up its memory-region, so every i.MX8ULP board can bring up the enclave with a single include instead of duplicating the reserved memory node. Include it from imx8ulp-evk. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> --- arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 3 ++- .../arm64/boot/dts/freescale/imx8ulp-firmware.dtsi | 31 ++++++++++++++++++++++ 2 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
index 4b925832bb66..5fe58a025cfd 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts@@ -1,12 +1,13 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright 2021 NXP + * Copyright 2021, 2025 NXP */ /dts-v1/; #include <dt-bindings/input/input.h> #include "imx8ulp.dtsi" +#include "imx8ulp-firmware.dtsi" / { model = "NXP i.MX8ULP EVK";
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-firmware.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp-firmware.dtsi
new file mode 100644
index 000000000000..e4bc352f68af
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8ulp-firmware.dtsi@@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + * + * Default reserved memory and EdgeLock Enclave (ELE) enablement shared by + * i.MX8ULP boards. Include this from a board dts to bring up the secure + * enclave without having to duplicate the reserved-memory node. The ELE + * hardware can only access DDR in the 0x80000000 - 0xafffffff window, so the + * pool is constrained to that range with alloc-ranges and the kernel is left + * to place the 1 MiB region. + */ + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ele_reserved: ele-reserved { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x30000000>; + size = <0 0x100000>; + no-map; + }; + }; +}; + +&hsm0 { + memory-region = <&ele_reserved>; + status = "okay"; +};
--
2.43.0