[PATCH 1/3] arm64: dts: mediatek: mt8195: Align ufshci node to dt-bindings changes
COLD25d
From: Louis-Alexis Eyraud <hidden>
Date: 2026-09-02 10:33:37
Also in:
linux-devicetree, linux-mediatek, lkml
Subsystem:
arm/mediatek soc support, the rest · Maintainers:
Matthias Brugger, AngeloGioacchino Del Regno, Linus Torvalds
The MT8195 UFS host controller dt bindings now describe several extra required clocks that were previously missing from clock description and deprecates the freq-table-hz property use in favour of operating-points-v2 instead. So, add in ufshci node the rx_symbol clocks in clock list and replace freq-table-hz property by operating-points-v2 one with a valid OPP table. Also reorder properties in node. Signed-off-by: Louis-Alexis Eyraud <redacted> --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 35 ++++++++++++++++++++++---------- 1 file changed, 24 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 9aaf8b6edcb5..c859f4283388 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi@@ -1472,8 +1472,7 @@ mmc2: mmc@11250000 { ufshci: ufshci@11270000 { compatible = "mediatek,mt8195-ufshci"; reg = <0 0x11270000 0 0x2300>; - interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH 0>; - phys = <&ufsphy>; + clocks = <&infracfg_ao CLK_INFRA_AO_AES_UFSFDE>, <&infracfg_ao CLK_INFRA_AO_AES>, <&infracfg_ao CLK_INFRA_AO_UFS_TICK>,
@@ -1481,17 +1480,31 @@ ufshci: ufshci@11270000 { <&infracfg_ao CLK_INFRA_AO_UNIPRO_TICK>, <&infracfg_ao CLK_INFRA_AO_UFS_MP_SAP_B>, <&infracfg_ao CLK_INFRA_AO_UFS_TX_SYMBOL>, - <&infracfg_ao CLK_INFRA_AO_PERI_UFS_MEM_SUB>; - clock-names = "ufs", "ufs_aes", "ufs_tick", - "unipro_sysclk", "unipro_tick", - "unipro_mp_bclk", "ufs_tx_symbol", - "ufs_mem_sub"; - freq-table-hz = <0 0>, <0 0>, <0 0>, - <0 0>, <0 0>, <0 0>, - <0 0>, <0 0>; - + <&infracfg_ao CLK_INFRA_AO_PERI_UFS_MEM_SUB>, + <&topckgen CLK_TOP_UFS_RX_SYMBOL>, + <&topckgen CLK_TOP_UFS_RX_SYMBOL1>; + clock-names = "main", "aes", "tick", "unipro_sysclk", + "unipro_tick", "unipro_mp_bclk", + "tx_symbol", "mem_sub", "rx_symbol0", + "rx_symbol1"; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH 0>; + operating-points-v2 = <&ufs_opp_table>; + phys = <&ufsphy>; mediatek,ufs-disable-mcq; status = "disabled"; + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-26000000 { + opp-hz = /bits/ 64 <26000000>, + /bits/ 64 <0>, /bits/ 64 <0>, + /bits/ 64 <0>, /bits/ 64 <0>, + /bits/ 64 <0>, /bits/ 64 <0>, + /bits/ 64 <0>, /bits/ 64 <0>, + /bits/ 64 <0>; + }; + }; }; lvts_mcu: thermal-sensor@11278000 {
--
2.55.0