On Thu, Aug 27, 2026 at 6:57 PM Chen-Yu Tsai [off-list ref] wrote:
The period value stored in the register is the number of clock cycles - 1.
Account for the offset when calculating the period in nanoseconds. This
fixes the discrepancy reported by the pwm core when CONFIG_PWM_DEBUG=1:
mediatek-disp-pwm 1100e000.pwm: .apply is not idempotent
(ena=1 pol=0 281500/499875) -> (ena=1 pol=0 281500/499750)
Calculation discrepancy in the driver was found by AI run by a colleague
while debugging another PWM related issue. Check against SoC datasheet
and fix done by the author.
Fixes: 3f2b16734914 ("pwm: mtk-disp: Implement atomic API .get_state()")
Cc: Jitao Shi <redacted>
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Fei Shao <redacted>