[PATCH v3 5/5] arm64: dts: rockchip: add ISP nodes to rk3588
From: Paul Elder <paul.elder@ideasonboard.com>
Date: 2026-08-27 10:49:34
Also in:
linux-devicetree, linux-media, linux-rockchip, lkml
Subsystem:
the rest · Maintainer:
Linus Torvalds
From: Xu Hongfei <redacted> Add device tree nodes for the ISP and their iommus on the RK3588. Signed-off-by: Xu Hongfei <redacted> Signed-off-by: Paul Elder <paul.elder@ideasonboard.com> --- Changes in v3: - reorder patches No change in v2 --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 57 +++++++++++++++++++++++++++ 1 file changed, 57 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index fc1fdbfd316223f8fbddfcf6cb3f1863cd8957d4..22b78465a82356361cd00ba363ee0163c7500667 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi@@ -3590,6 +3590,63 @@ gpio4: gpio@fec50000 { #interrupt-cells = <2>; }; }; + + isp0: isp@fdcb0000 { + compatible = "rockchip,rk3588-isp"; + reg = <0x0 0xfdcb0000 0x0 0x7f00>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "isp_irq", "mi_irq"; + clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>, + <&cru CLK_ISP0_CORE>, <&cru CLK_ISP0_CORE_MARVIN>, + <&cru CLK_ISP0_CORE_VICAP>; + clock-names = "aclk", "hclk", "clk_core", + "clk_core_marvin", "clk_core_vicap"; + power-domains = <&power RK3588_PD_VI>; + iommus = <&isp0_mmu>; + status = "disabled"; + }; + + isp0_mmu: iommu@fdcb7f00 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdcb7f00 0x0 0x100>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_VI>; + #iommu-cells = <0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + + isp1: isp@fdcc0000 { + compatible = "rockchip,rk3588-isp"; + reg = <0x0 0xfdcc0000 0x0 0x7f00>; + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "isp_irq", "mi_irq"; + clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>, + <&cru CLK_ISP1_CORE>, <&cru CLK_ISP1_CORE_MARVIN>, + <&cru CLK_ISP1_CORE_VICAP>; + clock-names = "aclk", "hclk", "clk_core", + "clk_core_marvin", "clk_core_vicap"; + power-domains = <&power RK3588_PD_ISP1>; + iommus = <&isp1_mmu>; + status = "disabled"; + }; + + isp1_mmu: iommu@fdcc7f00 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdcc7f00 0x0 0x100>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_ISP1>; + #iommu-cells = <0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; }; #include "rk3588-base-pinctrl.dtsi"
--
2.47.2