[PATCH 1/2] ARM: dts: ux500: Add the Imagis ISA to Janice DTS
From: Linus Walleij <linusw@kernel.org>
Date: 2026-08-24 22:51:33
Also in:
linux-devicetree
Subsystem:
arm/nomadik/ux500 architectures, the rest · Maintainers:
Linus Walleij, Linus Torvalds
This adds the Imagis ISA1200 haptic feedback chip to the Janice device tree. Signed-off-by: Linus Walleij <redacted> --- arch/arm/boot/dts/st/ste-ux500-samsung-janice.dts | 56 ++++++++++++++++++++++- 1 file changed, 55 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/st/ste-ux500-samsung-janice.dts b/arch/arm/boot/dts/st/ste-ux500-samsung-janice.dts
index 18fb7263058e..1f47d5910c9a 100644
--- a/arch/arm/boot/dts/st/ste-ux500-samsung-janice.dts
+++ b/arch/arm/boot/dts/st/ste-ux500-samsung-janice.dts@@ -360,7 +360,38 @@ i2c-gpio-2 { pinctrl-0 = <&i2c_gpio_2_default>; #address-cells = <1>; #size-cells = <0>; - /* TODO: add the Immersion ISA1200 I2C device here */ + + /* Haptic feedback unit Imagis ISA1200 */ + haptic-engine@49 { + compatible = "imagis,isa1200"; + reg = <0x49>; + + /* + * GPIO194 pin HEN (motor hardware enable) + * GPIO195 pin LEN (motor LDO enable) + */ + control-gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>, <&gpio6 3 GPIO_ACTIVE_HIGH>; + + /* clkout1 from ACLK divided by 8 */ + clocks = <&clkout_clk DB8500_CLKOUT_1 DB8500_CLKOUT_SRC_ACLK 8>; + + imagis,clk-div = <256>; + imagis,pll-div = <2>; + + imagis,mode = <0>; /* LRA_MODE */ + + imagis,period-ns = <13400>; + imagis,duty-cycle-ns = <100>; + + pinctrl-names = "default"; + pinctrl-0 = <&isa1200_janice_default>; + + ldo { + regulator-name = "vdd_vib"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + }; }; /* Bit-banged I2C on GPIO151 and GPIO152 also called "NFC_I2C" */
@@ -996,4 +1027,27 @@ janice_cfg3 { }; }; }; + isa1200 { + isa1200_janice_default: isa1200_janice { + /* Bring out clkout1 on pin GPIO227 pin AH7 */ + janice_mux { + function = "clkout"; + groups = "clkout1_a_1"; + }; + janice_cfg1 { + pins = "GPIO227_AH7"; + ste,config = <&out_lo>; + }; + /* HEN GPIO */ + janice_cfg2 { + pins = "GPIO194_AF27"; + ste,config = <&gpio_out_lo>; + }; + /* LEN GPIO */ + janice_cfg3 { + pins = "GPIO195_AG28"; + ste,config = <&gpio_out_lo>; + }; + }; + }; };
--
2.55.0