RE: [PATCH v3 23/23] mtd: spi-nor: debugfs: Expose SR opcodes and QE mask
From: <Takahiro.Kuwano@infineon.com>
Date: 2026-08-20 07:03:48
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Hi Miquel,
Expose Status Register opcodes based on the flash capabilities discovered while parsing the SFDP QER field. Value '0' indicates an absence of opcode (non supported), we do not print anything in that case. The QE bit is also displayed. Example on a W25Q02JV-M: $ grep opcodes -A10 /sys/kernel/debug/spi-nor/spi0.0/params opcodes read 0xec dummy cycles 6 erase 0xdc program 0x34 SR1 read 0x05 SR2 read 0x35 SR1+SR2 write 0x01 QE SR2 bit 1 8D extension none Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
S25HL512T: opcodes read 0xec dummy cycles 10 erase 0xd8 program 0x12 SR1 read 0x05 SR2 read 0x35 SR1+SR2 write 0x01 QE SR2 bit 1 8D extension repeat S25FS512S: opcodes read 0xec dummy cycles 10 erase 0xdc program 0x12 SR1 read 0x05 SR2 read 0x35 SR1+SR2 write 0x01 QE SR2 bit 1 8D extension none S25FL256S (no SFDP): opcodes read 0x6c dummy cycles 8 erase 0xdc program 0x12 SR1 read 0x05 SR2 read 0x35 SR1+SR2 write 0x01 QE SR2 bit 1 8D extension none S28HS512T (Octal, no QE): opcodes read 0xee dummy cycles 24 erase 0xd8 program 0x12 SR1 read 0x05 SR2 read 0x35 SR1 write 0x01 SR1+SR2 write 0x01 8D extension repeat Tested-by: Takahiro Kuwano <takahiro.kuwano@infineon.com>