[PATCH 4/8] arm64: dts: exynos: Re-order clocks and align continued properties
From: Krzysztof Kozlowski <hidden>
Date: 2026-07-26 17:44:29
Also in:
linux-devicetree, linux-samsung-soc, lkml
Subsystem:
arm/samsung s3c, s5p and exynos arm architectures, the rest · Maintainers:
Krzysztof Kozlowski, Peter Griffin, Linus Torvalds
Trivial white-space only changes to adjust to DTS coding style (clocks-names should follow clocks) and fix dt-check-style strict warnings like: [property-order] property 'clocks' out of canonical order (should sort before 'clock-names') [continuation-alignment] continuation should align to column 39 (under < or ") Signed-off-by: Krzysztof Kozlowski <redacted> --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 282 ++++++++++++++--------------- 1 file changed, 141 insertions(+), 141 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 875e75759f20..4d035c805aa6 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi@@ -400,14 +400,14 @@ cmu_top: clock-controller@10030000 { reg = <0x10030000 0x1000>; #clock-cells = <1>; - clock-names = "oscclk", - "sclk_mphy_pll", - "sclk_mfc_pll", - "sclk_bus_pll"; clocks = <&xxti>, - <&cmu_cpif CLK_SCLK_MPHY_PLL>, - <&cmu_mif CLK_SCLK_MFC_PLL>, - <&cmu_mif CLK_SCLK_BUS_PLL>; + <&cmu_cpif CLK_SCLK_MPHY_PLL>, + <&cmu_mif CLK_SCLK_MFC_PLL>, + <&cmu_mif CLK_SCLK_BUS_PLL>; + clock-names = "oscclk", + "sclk_mphy_pll", + "sclk_mfc_pll", + "sclk_bus_pll"; }; cmu_cpif: clock-controller@10fc0000 {
@@ -415,8 +415,8 @@ cmu_cpif: clock-controller@10fc0000 { reg = <0x10fc0000 0x1000>; #clock-cells = <1>; - clock-names = "oscclk"; clocks = <&xxti>; + clock-names = "oscclk"; }; cmu_mif: clock-controller@105b0000 {
@@ -424,10 +424,10 @@ cmu_mif: clock-controller@105b0000 { reg = <0x105b0000 0x2000>; #clock-cells = <1>; - clock-names = "oscclk", - "sclk_mphy_pll"; clocks = <&xxti>, - <&cmu_cpif CLK_SCLK_MPHY_PLL>; + <&cmu_cpif CLK_SCLK_MPHY_PLL>; + clock-names = "oscclk", + "sclk_mphy_pll"; }; cmu_peric: clock-controller@14c80000 {
@@ -447,26 +447,26 @@ cmu_fsys: clock-controller@156e0000 { reg = <0x156e0000 0x1000>; #clock-cells = <1>; - clock-names = "oscclk", - "sclk_ufs_mphy", - "aclk_fsys_200", - "sclk_pcie_100_fsys", - "sclk_ufsunipro_fsys", - "sclk_mmc2_fsys", - "sclk_mmc1_fsys", - "sclk_mmc0_fsys", - "sclk_usbhost30_fsys", - "sclk_usbdrd30_fsys"; clocks = <&xxti>, - <&cmu_cpif CLK_SCLK_UFS_MPHY>, - <&cmu_top CLK_ACLK_FSYS_200>, - <&cmu_top CLK_SCLK_PCIE_100_FSYS>, - <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>, - <&cmu_top CLK_SCLK_MMC2_FSYS>, - <&cmu_top CLK_SCLK_MMC1_FSYS>, - <&cmu_top CLK_SCLK_MMC0_FSYS>, - <&cmu_top CLK_SCLK_USBHOST30_FSYS>, - <&cmu_top CLK_SCLK_USBDRD30_FSYS>; + <&cmu_cpif CLK_SCLK_UFS_MPHY>, + <&cmu_top CLK_ACLK_FSYS_200>, + <&cmu_top CLK_SCLK_PCIE_100_FSYS>, + <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>, + <&cmu_top CLK_SCLK_MMC2_FSYS>, + <&cmu_top CLK_SCLK_MMC1_FSYS>, + <&cmu_top CLK_SCLK_MMC0_FSYS>, + <&cmu_top CLK_SCLK_USBHOST30_FSYS>, + <&cmu_top CLK_SCLK_USBDRD30_FSYS>; + clock-names = "oscclk", + "sclk_ufs_mphy", + "aclk_fsys_200", + "sclk_pcie_100_fsys", + "sclk_ufsunipro_fsys", + "sclk_mmc2_fsys", + "sclk_mmc1_fsys", + "sclk_mmc0_fsys", + "sclk_usbhost30_fsys", + "sclk_usbdrd30_fsys"; }; cmu_g2d: clock-controller@12460000 {
@@ -474,12 +474,12 @@ cmu_g2d: clock-controller@12460000 { reg = <0x12460000 0x1000>; #clock-cells = <1>; - clock-names = "oscclk", - "aclk_g2d_266", - "aclk_g2d_400"; clocks = <&xxti>, - <&cmu_top CLK_ACLK_G2D_266>, - <&cmu_top CLK_ACLK_G2D_400>; + <&cmu_top CLK_ACLK_G2D_266>, + <&cmu_top CLK_ACLK_G2D_400>; + clock-names = "oscclk", + "aclk_g2d_266", + "aclk_g2d_400"; power-domains = <&pd_g2d>; };
@@ -488,24 +488,24 @@ cmu_disp: clock-controller@13b90000 { reg = <0x13b90000 0x1000>; #clock-cells = <1>; - clock-names = "oscclk", - "sclk_dsim1_disp", - "sclk_dsim0_disp", - "sclk_dsd_disp", - "sclk_decon_tv_eclk_disp", - "sclk_decon_vclk_disp", - "sclk_decon_eclk_disp", - "sclk_decon_tv_vclk_disp", - "aclk_disp_333"; clocks = <&xxti>, - <&cmu_mif CLK_SCLK_DSIM1_DISP>, - <&cmu_mif CLK_SCLK_DSIM0_DISP>, - <&cmu_mif CLK_SCLK_DSD_DISP>, - <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, - <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>, - <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, - <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>, - <&cmu_mif CLK_ACLK_DISP_333>; + <&cmu_mif CLK_SCLK_DSIM1_DISP>, + <&cmu_mif CLK_SCLK_DSIM0_DISP>, + <&cmu_mif CLK_SCLK_DSD_DISP>, + <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, + <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>, + <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, + <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>, + <&cmu_mif CLK_ACLK_DISP_333>; + clock-names = "oscclk", + "sclk_dsim1_disp", + "sclk_dsim0_disp", + "sclk_dsd_disp", + "sclk_decon_tv_eclk_disp", + "sclk_decon_vclk_disp", + "sclk_decon_eclk_disp", + "sclk_decon_tv_vclk_disp", + "aclk_disp_333"; power-domains = <&pd_disp>; };
@@ -513,8 +513,8 @@ cmu_aud: clock-controller@114c0000 { compatible = "samsung,exynos5433-cmu-aud"; reg = <0x114c0000 0x1000>; #clock-cells = <1>; - clock-names = "oscclk", "fout_aud_pll"; clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>; + clock-names = "oscclk", "fout_aud_pll"; power-domains = <&pd_aud>; };
@@ -523,8 +523,8 @@ cmu_bus0: clock-controller@13600000 { reg = <0x13600000 0x1000>; #clock-cells = <1>; - clock-names = "aclk_bus0_400"; clocks = <&cmu_top CLK_ACLK_BUS0_400>; + clock-names = "aclk_bus0_400"; }; cmu_bus1: clock-controller@14800000 {
@@ -532,8 +532,8 @@ cmu_bus1: clock-controller@14800000 { reg = <0x14800000 0x1000>; #clock-cells = <1>; - clock-names = "aclk_bus1_400"; clocks = <&cmu_top CLK_ACLK_BUS1_400>; + clock-names = "aclk_bus1_400"; }; cmu_bus2: clock-controller@13400000 {
@@ -541,8 +541,8 @@ cmu_bus2: clock-controller@13400000 { reg = <0x13400000 0x1000>; #clock-cells = <1>; - clock-names = "oscclk", "aclk_bus2_400"; clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>; + clock-names = "oscclk", "aclk_bus2_400"; }; cmu_g3d: clock-controller@14aa0000 {
@@ -550,8 +550,8 @@ cmu_g3d: clock-controller@14aa0000 { reg = <0x14aa0000 0x2000>; #clock-cells = <1>; - clock-names = "oscclk", "aclk_g3d_400"; clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>; + clock-names = "oscclk", "aclk_g3d_400"; power-domains = <&pd_g3d>; };
@@ -560,12 +560,12 @@ cmu_gscl: clock-controller@13cf0000 { reg = <0x13cf0000 0x1000>; #clock-cells = <1>; - clock-names = "oscclk", - "aclk_gscl_111", - "aclk_gscl_333"; clocks = <&xxti>, - <&cmu_top CLK_ACLK_GSCL_111>, - <&cmu_top CLK_ACLK_GSCL_333>; + <&cmu_top CLK_ACLK_GSCL_111>, + <&cmu_top CLK_ACLK_GSCL_333>; + clock-names = "oscclk", + "aclk_gscl_111", + "aclk_gscl_333"; power-domains = <&pd_gscl>; };
@@ -574,8 +574,8 @@ cmu_apollo: clock-controller@11900000 { reg = <0x11900000 0x2000>; #clock-cells = <1>; - clock-names = "oscclk", "sclk_bus_pll_apollo"; clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>; + clock-names = "oscclk", "sclk_bus_pll_apollo"; }; cmu_atlas: clock-controller@11800000 {
@@ -583,8 +583,8 @@ cmu_atlas: clock-controller@11800000 { reg = <0x11800000 0x2000>; #clock-cells = <1>; - clock-names = "oscclk", "sclk_bus_pll_atlas"; clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>; + clock-names = "oscclk", "sclk_bus_pll_atlas"; }; cmu_mscl: clock-controller@150d0000 {
@@ -592,12 +592,12 @@ cmu_mscl: clock-controller@150d0000 { reg = <0x150d0000 0x1000>; #clock-cells = <1>; - clock-names = "oscclk", - "sclk_jpeg_mscl", - "aclk_mscl_400"; clocks = <&xxti>, - <&cmu_top CLK_SCLK_JPEG_MSCL>, - <&cmu_top CLK_ACLK_MSCL_400>; + <&cmu_top CLK_SCLK_JPEG_MSCL>, + <&cmu_top CLK_ACLK_MSCL_400>; + clock-names = "oscclk", + "sclk_jpeg_mscl", + "aclk_mscl_400"; power-domains = <&pd_mscl>; };
@@ -606,8 +606,8 @@ cmu_mfc: clock-controller@15280000 { reg = <0x15280000 0x1000>; #clock-cells = <1>; - clock-names = "oscclk", "aclk_mfc_400"; clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>; + clock-names = "oscclk", "aclk_mfc_400"; power-domains = <&pd_mfc>; };
@@ -616,8 +616,8 @@ cmu_hevc: clock-controller@14f80000 { reg = <0x14f80000 0x1000>; #clock-cells = <1>; - clock-names = "oscclk", "aclk_hevc_400"; clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>; + clock-names = "oscclk", "aclk_hevc_400"; power-domains = <&pd_hevc>; };
@@ -626,12 +626,12 @@ cmu_isp: clock-controller@146d0000 { reg = <0x146d0000 0x1000>; #clock-cells = <1>; - clock-names = "oscclk", - "aclk_isp_dis_400", - "aclk_isp_400"; clocks = <&xxti>, - <&cmu_top CLK_ACLK_ISP_DIS_400>, - <&cmu_top CLK_ACLK_ISP_400>; + <&cmu_top CLK_ACLK_ISP_DIS_400>, + <&cmu_top CLK_ACLK_ISP_400>; + clock-names = "oscclk", + "aclk_isp_dis_400", + "aclk_isp_400"; power-domains = <&pd_isp>; };
@@ -640,14 +640,14 @@ cmu_cam0: clock-controller@120d0000 { reg = <0x120d0000 0x1000>; #clock-cells = <1>; - clock-names = "oscclk", - "aclk_cam0_333", - "aclk_cam0_400", - "aclk_cam0_552"; clocks = <&xxti>, - <&cmu_top CLK_ACLK_CAM0_333>, - <&cmu_top CLK_ACLK_CAM0_400>, - <&cmu_top CLK_ACLK_CAM0_552>; + <&cmu_top CLK_ACLK_CAM0_333>, + <&cmu_top CLK_ACLK_CAM0_400>, + <&cmu_top CLK_ACLK_CAM0_552>; + clock-names = "oscclk", + "aclk_cam0_333", + "aclk_cam0_400", + "aclk_cam0_552"; power-domains = <&pd_cam0>; };
@@ -656,20 +656,20 @@ cmu_cam1: clock-controller@145d0000 { reg = <0x145d0000 0x1000>; #clock-cells = <1>; - clock-names = "oscclk", - "sclk_isp_uart_cam1", - "sclk_isp_spi1_cam1", - "sclk_isp_spi0_cam1", - "aclk_cam1_333", - "aclk_cam1_400", - "aclk_cam1_552"; clocks = <&xxti>, - <&cmu_top CLK_SCLK_ISP_UART_CAM1>, - <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>, - <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>, - <&cmu_top CLK_ACLK_CAM1_333>, - <&cmu_top CLK_ACLK_CAM1_400>, - <&cmu_top CLK_ACLK_CAM1_552>; + <&cmu_top CLK_SCLK_ISP_UART_CAM1>, + <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>, + <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>, + <&cmu_top CLK_ACLK_CAM1_333>, + <&cmu_top CLK_ACLK_CAM1_400>, + <&cmu_top CLK_ACLK_CAM1_552>; + clock-names = "oscclk", + "sclk_isp_uart_cam1", + "sclk_isp_spi1_cam1", + "sclk_isp_spi0_cam1", + "aclk_cam1_333", + "aclk_cam1_400", + "aclk_cam1_552"; power-domains = <&pd_cam1>; };
@@ -678,23 +678,23 @@ cmu_imem: clock-controller@11060000 { reg = <0x11060000 0x1000>; #clock-cells = <1>; - clock-names = "oscclk", - "aclk_imem_sssx_266", - "aclk_imem_266", - "aclk_imem_200"; clocks = <&xxti>, - <&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>, - <&cmu_top CLK_DIV_ACLK_IMEM_266>, - <&cmu_top CLK_DIV_ACLK_IMEM_200>; + <&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>, + <&cmu_top CLK_DIV_ACLK_IMEM_266>, + <&cmu_top CLK_DIV_ACLK_IMEM_200>; + clock-names = "oscclk", + "aclk_imem_sssx_266", + "aclk_imem_266", + "aclk_imem_200"; }; slim_sss: slim-sss@11140000 { compatible = "samsung,exynos5433-slim-sss"; reg = <0x11140000 0x1000>; interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "pclk", "aclk"; clocks = <&cmu_imem CLK_PCLK_SLIMSSS>, <&cmu_imem CLK_ACLK_SLIMSSS>; + clock-names = "pclk", "aclk"; }; pd_gscl: power-domain@105c4000 {
@@ -955,8 +955,8 @@ pmu_system_controller: system-controller@105c0000 { compatible = "samsung,exynos5433-pmu", "simple-mfd", "syscon"; reg = <0x105c0000 0x5008>; #clock-cells = <1>; - clock-names = "clkout16"; clocks = <&xxti>; + clock-names = "clkout16"; mipi_phy: mipi-phy { compatible = "samsung,exynos5433-mipi-video-phy";
@@ -976,13 +976,13 @@ reboot: syscon-reboot { gic: interrupt-controller@11001000 { compatible = "arm,gic-400"; + reg = <0x11001000 0x1000>, + <0x11002000 0x2000>, + <0x11004000 0x2000>, + <0x11006000 0x2000>; #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; - reg = <0x11001000 0x1000>, - <0x11002000 0x2000>, - <0x11004000 0x2000>, - <0x11006000 0x2000>; interrupts = <GIC_PPI 9 0xf04>; };
@@ -1191,13 +1191,13 @@ gsc_0: video-scaler@13c00000 { compatible = "samsung,exynos5433-gsc"; reg = <0x13c00000 0x1000>; interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "pclk", "aclk", "aclk_xiu", - "aclk_gsclbend", "gsd"; clocks = <&cmu_gscl CLK_PCLK_GSCL0>, <&cmu_gscl CLK_ACLK_GSCL0>, <&cmu_gscl CLK_ACLK_XIU_GSCLX>, <&cmu_gscl CLK_ACLK_GSCLBEND_333>, <&cmu_gscl CLK_ACLK_GSD>; + clock-names = "pclk", "aclk", "aclk_xiu", + "aclk_gsclbend", "gsd"; iommus = <&sysmmu_gscl0>; power-domains = <&pd_gscl>; };
@@ -1206,13 +1206,13 @@ gsc_1: video-scaler@13c10000 { compatible = "samsung,exynos5433-gsc"; reg = <0x13c10000 0x1000>; interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "pclk", "aclk", "aclk_xiu", - "aclk_gsclbend", "gsd"; clocks = <&cmu_gscl CLK_PCLK_GSCL1>, <&cmu_gscl CLK_ACLK_GSCL1>, <&cmu_gscl CLK_ACLK_XIU_GSCLX>, <&cmu_gscl CLK_ACLK_GSCLBEND_333>, <&cmu_gscl CLK_ACLK_GSD>; + clock-names = "pclk", "aclk", "aclk_xiu", + "aclk_gsclbend", "gsd"; iommus = <&sysmmu_gscl1>; power-domains = <&pd_gscl>; };
@@ -1221,13 +1221,13 @@ gsc_2: video-scaler@13c20000 { compatible = "samsung,exynos5433-gsc"; reg = <0x13c20000 0x1000>; interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "pclk", "aclk", "aclk_xiu", - "aclk_gsclbend", "gsd"; clocks = <&cmu_gscl CLK_PCLK_GSCL2>, <&cmu_gscl CLK_ACLK_GSCL2>, <&cmu_gscl CLK_ACLK_XIU_GSCLX>, <&cmu_gscl CLK_ACLK_GSCLBEND_333>, <&cmu_gscl CLK_ACLK_GSD>; + clock-names = "pclk", "aclk", "aclk_xiu", + "aclk_gsclbend", "gsd"; iommus = <&sysmmu_gscl2>; power-domains = <&pd_gscl>; };
@@ -1295,10 +1295,10 @@ scaler_0: scaler@15000000 { compatible = "samsung,exynos5433-scaler"; reg = <0x15000000 0x1294>; interrupts = <0 402 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "pclk", "aclk", "aclk_xiu"; clocks = <&cmu_mscl CLK_PCLK_M2MSCALER0>, <&cmu_mscl CLK_ACLK_M2MSCALER0>, <&cmu_mscl CLK_ACLK_XIU_MSCLX>; + clock-names = "pclk", "aclk", "aclk_xiu"; iommus = <&sysmmu_scaler_0>; power-domains = <&pd_mscl>; };
@@ -1307,10 +1307,10 @@ scaler_1: scaler@15010000 { compatible = "samsung,exynos5433-scaler"; reg = <0x15010000 0x1294>; interrupts = <0 403 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "pclk", "aclk", "aclk_xiu"; clocks = <&cmu_mscl CLK_PCLK_M2MSCALER1>, <&cmu_mscl CLK_ACLK_M2MSCALER1>, <&cmu_mscl CLK_ACLK_XIU_MSCLX>; + clock-names = "pclk", "aclk", "aclk_xiu"; iommus = <&sysmmu_scaler_1>; power-domains = <&pd_mscl>; };
@@ -1319,11 +1319,11 @@ jpeg: codec@15020000 { compatible = "samsung,exynos5433-jpeg"; reg = <0x15020000 0x10000>; interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "pclk", "aclk", "aclk_xiu", "sclk"; clocks = <&cmu_mscl CLK_PCLK_JPEG>, <&cmu_mscl CLK_ACLK_JPEG>, <&cmu_mscl CLK_ACLK_XIU_MSCLX>, <&cmu_mscl CLK_SCLK_JPEG>; + clock-names = "pclk", "aclk", "aclk_xiu", "sclk"; iommus = <&sysmmu_jpeg>; power-domains = <&pd_mscl>; };
@@ -1332,10 +1332,10 @@ mfc: codec@152e0000 { compatible = "samsung,exynos5433-mfc"; reg = <0x152e0000 0x10000>; interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "pclk", "aclk", "aclk_xiu"; clocks = <&cmu_mfc CLK_PCLK_MFC>, <&cmu_mfc CLK_ACLK_MFC>, <&cmu_mfc CLK_ACLK_XIU_MFCX>; + clock-names = "pclk", "aclk", "aclk_xiu"; iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>; iommu-names = "left", "right"; power-domains = <&pd_mfc>;
@@ -1345,9 +1345,9 @@ sysmmu_decon0x: sysmmu@13a00000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13a00000 0x1000>; interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "aclk", "pclk"; clocks = <&cmu_disp CLK_ACLK_SMMU_DECON0X>, - <&cmu_disp CLK_PCLK_SMMU_DECON0X>; + <&cmu_disp CLK_PCLK_SMMU_DECON0X>; + clock-names = "aclk", "pclk"; power-domains = <&pd_disp>; #iommu-cells = <0>; };
@@ -1356,9 +1356,9 @@ sysmmu_decon1x: sysmmu@13a10000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13a10000 0x1000>; interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "aclk", "pclk"; clocks = <&cmu_disp CLK_ACLK_SMMU_DECON1X>, - <&cmu_disp CLK_PCLK_SMMU_DECON1X>; + <&cmu_disp CLK_PCLK_SMMU_DECON1X>; + clock-names = "aclk", "pclk"; #iommu-cells = <0>; power-domains = <&pd_disp>; };
@@ -1367,9 +1367,9 @@ sysmmu_tv0x: sysmmu@13a20000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13a20000 0x1000>; interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "aclk", "pclk"; clocks = <&cmu_disp CLK_ACLK_SMMU_TV0X>, - <&cmu_disp CLK_PCLK_SMMU_TV0X>; + <&cmu_disp CLK_PCLK_SMMU_TV0X>; + clock-names = "aclk", "pclk"; #iommu-cells = <0>; power-domains = <&pd_disp>; };
@@ -1378,9 +1378,9 @@ sysmmu_tv1x: sysmmu@13a30000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13a30000 0x1000>; interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "aclk", "pclk"; clocks = <&cmu_disp CLK_ACLK_SMMU_TV1X>, - <&cmu_disp CLK_PCLK_SMMU_TV1X>; + <&cmu_disp CLK_PCLK_SMMU_TV1X>; + clock-names = "aclk", "pclk"; #iommu-cells = <0>; power-domains = <&pd_disp>; };
@@ -1389,9 +1389,9 @@ sysmmu_gscl0: sysmmu@13c80000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13c80000 0x1000>; interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "aclk", "pclk"; clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL0>, <&cmu_gscl CLK_PCLK_SMMU_GSCL0>; + clock-names = "aclk", "pclk"; #iommu-cells = <0>; power-domains = <&pd_gscl>; };
@@ -1400,9 +1400,9 @@ sysmmu_gscl1: sysmmu@13c90000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13c90000 0x1000>; interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "aclk", "pclk"; clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL1>, <&cmu_gscl CLK_PCLK_SMMU_GSCL1>; + clock-names = "aclk", "pclk"; #iommu-cells = <0>; power-domains = <&pd_gscl>; };
@@ -1411,9 +1411,9 @@ sysmmu_gscl2: sysmmu@13ca0000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13ca0000 0x1000>; interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "aclk", "pclk"; clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL2>, <&cmu_gscl CLK_PCLK_SMMU_GSCL2>; + clock-names = "aclk", "pclk"; #iommu-cells = <0>; power-domains = <&pd_gscl>; };
@@ -1422,9 +1422,9 @@ sysmmu_scaler_0: sysmmu@15040000 { compatible = "samsung,exynos-sysmmu"; reg = <0x15040000 0x1000>; interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "aclk", "pclk"; clocks = <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER0>, - <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER0>; + <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER0>; + clock-names = "aclk", "pclk"; #iommu-cells = <0>; power-domains = <&pd_mscl>; };
@@ -1433,9 +1433,9 @@ sysmmu_scaler_1: sysmmu@15050000 { compatible = "samsung,exynos-sysmmu"; reg = <0x15050000 0x1000>; interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "aclk", "pclk"; clocks = <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER1>, - <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER1>; + <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER1>; + clock-names = "aclk", "pclk"; #iommu-cells = <0>; power-domains = <&pd_mscl>; };
@@ -1444,9 +1444,9 @@ sysmmu_jpeg: sysmmu@15060000 { compatible = "samsung,exynos-sysmmu"; reg = <0x15060000 0x1000>; interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "aclk", "pclk"; clocks = <&cmu_mscl CLK_ACLK_SMMU_JPEG>, - <&cmu_mscl CLK_PCLK_SMMU_JPEG>; + <&cmu_mscl CLK_PCLK_SMMU_JPEG>; + clock-names = "aclk", "pclk"; #iommu-cells = <0>; power-domains = <&pd_mscl>; };
@@ -1455,9 +1455,9 @@ sysmmu_mfc_0: sysmmu@15200000 { compatible = "samsung,exynos-sysmmu"; reg = <0x15200000 0x1000>; interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "aclk", "pclk"; clocks = <&cmu_mfc CLK_ACLK_SMMU_MFC_0>, - <&cmu_mfc CLK_PCLK_SMMU_MFC_0>; + <&cmu_mfc CLK_PCLK_SMMU_MFC_0>; + clock-names = "aclk", "pclk"; #iommu-cells = <0>; power-domains = <&pd_mfc>; };
@@ -1466,9 +1466,9 @@ sysmmu_mfc_1: sysmmu@15210000 { compatible = "samsung,exynos-sysmmu"; reg = <0x15210000 0x1000>; interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "aclk", "pclk"; clocks = <&cmu_mfc CLK_ACLK_SMMU_MFC_1>, - <&cmu_mfc CLK_PCLK_SMMU_MFC_1>; + <&cmu_mfc CLK_PCLK_SMMU_MFC_1>; + clock-names = "aclk", "pclk"; #iommu-cells = <0>; power-domains = <&pd_mfc>; };
@@ -1621,8 +1621,8 @@ adc: adc@14d10000 { compatible = "samsung,exynos5433-adc", "samsung,exynos7-adc"; reg = <0x14d10000 0x100>; interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "adc"; clocks = <&cmu_peric CLK_PCLK_ADCIF>; + clock-names = "adc"; #io-channel-cells = <1>; status = "disabled";
--
2.53.0