[PATCH v2 2/7] clk: qcom: clean-up simple provider misuse of the consumer API
From: Jerome Brunet <jbrunet@baylibre.com>
Date: 2026-07-24 09:04:31
Also in:
linux-arm-msm, linux-clk, linux-omap, linux-renesas-soc, linux-rockchip, linux-tegra, lkml
Subsystem:
arm/qualcomm mailing list, common clk framework, qualcomm clock drivers, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Bjorn Andersson, Linus Torvalds
Clock provider should not be using the consumer interface. In other words, a provider should not be dealing with struct clk. This change targets occurrences for which the provider uses the consumer interface and corresponding clk_hw interface exist. Reviewed-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> --- drivers/clk/qcom/clk-hfpll.c | 4 ++-- drivers/clk/qcom/clk-krait.c | 2 +- drivers/clk/qcom/clk-rcg.c | 4 ++-- drivers/clk/qcom/clk-rcg2.c | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/qcom/clk-hfpll.c b/drivers/clk/qcom/clk-hfpll.c
index 705352aff067..9e9118d24df7 100644
--- a/drivers/clk/qcom/clk-hfpll.c
+++ b/drivers/clk/qcom/clk-hfpll.c@@ -166,7 +166,7 @@ static int clk_hfpll_set_rate(struct clk_hw *hw, unsigned long rate, spin_lock_irqsave(&h->lock, flags); - enabled = __clk_is_enabled(hw->clk); + enabled = clk_hw_is_enabled(hw); if (enabled) __clk_hfpll_disable(h);
@@ -220,7 +220,7 @@ static int clk_hfpll_init(struct clk_hw *hw) regmap_read(regmap, hd->status_reg, &status); if (!(status & BIT(hd->lock_bit))) { WARN(1, "HFPLL %s is ON, but not locked!\n", - __clk_get_name(hw->clk)); + clk_hw_get_name(hw)); clk_hfpll_disable(hw); __clk_hfpll_init_once(hw); }
diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c
index f5ce403e1e27..5e4408b7445d 100644
--- a/drivers/clk/qcom/clk-krait.c
+++ b/drivers/clk/qcom/clk-krait.c@@ -68,7 +68,7 @@ static int krait_mux_set_parent(struct clk_hw *hw, u8 index) sel = clk_mux_index_to_val(mux->parent_map, 0, index); mux->en_mask = sel; /* Don't touch mux if CPU is off as it won't work */ - if (__clk_is_enabled(hw->clk)) + if (clk_hw_is_enabled(hw)) __krait_mux_set_sel(mux, sel); mux->reparent = true;
diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c
index 31f0650b48ba..1664101e8f78 100644
--- a/drivers/clk/qcom/clk-rcg.c
+++ b/drivers/clk/qcom/clk-rcg.c@@ -208,7 +208,7 @@ static int configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f) bool banked_p = !!rcg->p[1].pre_div_width; struct clk_hw *hw = &rcg->clkr.hw; - enabled = __clk_is_enabled(hw->clk); + enabled = clk_hw_is_enabled(hw); ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®); if (ret)
@@ -771,7 +771,7 @@ static int clk_rcg_lcc_set_rate(struct clk_hw *hw, unsigned long rate, regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0); ret = __clk_rcg_set_rate(rcg, f); /* Switch back to M/N if it's clocking */ - if (__clk_is_enabled(hw->clk)) + if (clk_hw_is_enabled(hw)) regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm); return ret;
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 6064a0e17d51..d7914e59129f 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c@@ -489,7 +489,7 @@ static int clk_rcg2_determine_gp_rate(struct clk_hw *hw, u64 parent_rate; parent = clk_hw_get_parent(hw); - parent_rate = clk_get_rate(parent->clk); + parent_rate = clk_hw_get_rate(parent); if (!parent_rate) return -EINVAL;
--
2.47.3