[PATCH v4 6/6] arm64: cpufeature: Detect BBML3 based on ID_AA64MMFR2_EL1.BBM
From: Linu Cherian <hidden>
Date: 2026-07-23 04:42:20
Also in:
lkml
Subsystem:
arm64 port (aarch64 architecture), the rest · Maintainers:
Catalin Marinas, Will Deacon, Linus Torvalds
Add ID_AA64MMFR2_EL1.BBM based BBML3 feature detection in cpu_supports_bbml3() so that cpus with the feature would not have to be added into MIDR based supports_bbml3_list. Reviewed-by: Gavin Shan <redacted> Reviewed-by: Anshuman Khandual <redacted> Signed-off-by: Linu Cherian <redacted> --- arch/arm64/kernel/cpufeature.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 896bafdb00b1..dbd7d187520c 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c@@ -2133,6 +2133,12 @@ static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, bool cpu_supports_bbml3(void) { + u64 mmfr2; + + mmfr2 = __read_sysreg_by_encoding(SYS_ID_AA64MMFR2_EL1); + if (SYS_FIELD_GET(ID_AA64MMFR2_EL1, BBM, mmfr2) >= ID_AA64MMFR2_EL1_BBM_3) + return true; + /* CPUs that support BBML3 but dont advertise through ID_AA64MMFR2_EL1 */ static const struct midr_range supports_bbml3_list[] = { MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf),
@@ -2154,15 +2160,10 @@ bool cpu_supports_bbml3(void) {} }; - if (!is_midr_in_range_list(supports_bbml3_list)) - return false; - - /* - * We currently ignore the ID_AA64MMFR2_EL1 register, and only care - * about whether the MIDR check passes. - */ + if (is_midr_in_range_list(supports_bbml3_list)) + return true; - return true; + return false; } static bool has_bbml3(const struct arm64_cpu_capabilities *caps, int scope)
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2.43.0