[PATCH v4 1/3] dt-bindings: phy: nuvoton,ma35d1-usb2-phy: extend for dual-port and OTG
From: Joey Lu <hidden>
Date: 2026-07-20 10:22:33
Also in:
linux-devicetree, linux-phy, lkml
Subsystem:
arm/nuvoton ma35 architecture, generic phy framework, open firmware and flattened device tree bindings, the rest · Maintainers:
Jacky Huang, Shan-Chun Hung, Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
The MA35D1 exposes two USB PHY ports (PHY0 and PHY1) managed by the
same hardware block (USBPMISCR register in the system-management syscon).
PHY0 is shared between the DWC2 gadget controller and EHCI0/OHCI0
through an automatic hardware mux that follows the USB ID pin; PHY1 is
dedicated to EHCI1/OHCI1. Because both ports share the same register
topology a single binding and driver should cover both.
Changing '#phy-cells' from const: 0 to enum: [0, 1] lets consumers name
the port they need while preserving backward compatibility: boards already
using '#phy-cells = <0>' continue to validate and function unchanged.
The two new optional properties:
- nuvoton,rcalcode: the resistor calibration trim code is determined at
board design time to match the PCB trace impedance.
- nuvoton,oc-active-high: the over-current detect polarity depends on
the choice of VBUS power switch.
Signed-off-by: Joey Lu <redacted>
Reviewed-by: Krzysztof Kozlowski <redacted>
---
.../bindings/phy/nuvoton,ma35d1-usb2-phy.yaml | 44 ++++++++++++++++++-
1 file changed, 42 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/nuvoton,ma35d1-usb2-phy.yaml b/Documentation/devicetree/bindings/phy/nuvoton,ma35d1-usb2-phy.yaml
index fff858c909a0..1bd22dd0e5fc 100644
--- a/Documentation/devicetree/bindings/phy/nuvoton,ma35d1-usb2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/nuvoton,ma35d1-usb2-phy.yaml@@ -8,6 +8,18 @@ title: Nuvoton MA35D1 USB2 phy maintainers: - Hui-Ping Chen <hpchen0nvt@gmail.com> + - Joey Lu <yclu4@nuvoton.com> + +description: + USB 2.0 PHY for the Nuvoton MA35D1 SoC. The PHY node is a standalone + platform device that accesses the USB PHY control registers inside the + system-management syscon block via the nuvoton,sys phandle. + + PHY0 is the OTG port whose signals are routed to either the DWC2 gadget + controller or the EHCI0/OHCI0 host controller by a hardware mux that + follows the USB ID pin automatically. + + PHY1 is a dedicated host-only port used by EHCI1/OHCI1. properties: compatible:
@@ -15,7 +27,12 @@ properties: - nuvoton,ma35d1-usb2-phy "#phy-cells": - const: 0 + enum: [0, 1] + description: + When 0, the node exposes PHY0 only and consumers reference it + with no cell argument. When 1, the single cell selects the port, + with 0 for the OTG port (USB0, shared with DWC2 gadget controller) + and 1 for the host-only port (USB1). clocks: maxItems: 1
@@ -23,7 +40,29 @@ properties: nuvoton,sys: $ref: /schemas/types.yaml#/definitions/phandle description: - phandle to syscon for checking the PHY clock status. + Phandle to the system-management syscon node providing access to the + USB PHY control registers. + + nuvoton,rcalcode: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 2 + items: + minimum: 0 + maximum: 15 + description: + Resistor calibration trim codes for PHY0 and PHY1 respectively. + Each 4-bit value is written to the RCALCODE field in USBPMISCR and + adjusts the PHY's internal termination resistance. Both entries must + be supplied when this property is present; when absent the hardware + reset default is used for each port. + + nuvoton,oc-active-high: + type: boolean + description: + When present, the over-current detect input from the VBUS power switch + is treated as active-high. The default (property absent) is active-low. + This setting is shared by both USB host ports. required: - compatible
@@ -42,4 +81,5 @@ examples: clocks = <&clk USBD_GATE>; nuvoton,sys = <&sys>; #phy-cells = <0>; + nuvoton,rcalcode = <7 7>; };
--
2.43.0