[PATCH v2 4/7] dt-bindings: reset: Add reset controller constants for mt8167
From: Luca Leonardo Scorcia <hidden>
Date: 2026-07-17 16:42:13
Also in:
linux-devicetree, linux-mediatek, linux-watchdog, lkml
Subsystem:
open firmware and flattened device tree bindings, reset controller framework, the rest · Maintainers:
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Linus Torvalds
Add the various bits that identify watchdog and mmsys resets. IDs for mmsys resets restart from zero as they are used in a different device. Signed-off-by: Luca Leonardo Scorcia <redacted> --- .../reset/mediatek,mt8167-resets.h | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 include/dt-bindings/reset/mediatek,mt8167-resets.h
diff --git a/include/dt-bindings/reset/mediatek,mt8167-resets.h b/include/dt-bindings/reset/mediatek,mt8167-resets.h
new file mode 100644
index 000000000000..85d2d0e99c68
--- /dev/null
+++ b/include/dt-bindings/reset/mediatek,mt8167-resets.h@@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8167 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8167 + +/* TOPRGU resets, these are actual bits in the register */ +#define MT8167_TOPRGU_DDRPHY_FLASH_RST 0 +#define MT8167_TOPRGU_AUD_PAD_RST 1 +#define MT8167_TOPRGU_MM_RST 2 +#define MT8167_TOPRGU_MFG_RST 3 +#define MT8167_TOPRGU_MDSYS_RST 4 +#define MT8167_TOPRGU_CONN_RST 5 +#define MT8167_TOPRGU_PAD2CAM_DIG_MIPI_RX_RST 6 +#define MT8167_TOPRGU_DIG_MIPI_TX_RST 7 +#define MT8167_TOPRGU_SPI_PAD_MACRO_RST 8 +/* bit 9 is reserved, unused according to data sheet */ +#define MT8167_TOPRGU_APMIXED_RST 10 +#define MT8167_TOPRGU_VDEC_RST 11 +#define MT8167_TOPRGU_CONN_MCU_RST 12 +#define MT8167_TOPRGU_EFUSE_RST 13 +#define MT8167_TOPRGU_PWRAP_SPICTL_RST 14 +#define MT8167_TOPRGU_SW_RST_NUM 15 + +/* MMSYS resets, these are IDs */ +#define MT8167_MMSYS_SW0_RST_B_SMI_COMMON 0 +#define MT8167_MMSYS_SW0_RST_B_SMI_LARB0 1 +#define MT8167_MMSYS_SW0_RST_B_CAM_MDP 2 +#define MT8167_MMSYS_SW0_RST_B_MDP_RDMA0 3 +#define MT8167_MMSYS_SW0_RST_B_MDP_RSZ0 4 +#define MT8167_MMSYS_SW0_RST_B_MDP_RSZ1 5 +#define MT8167_MMSYS_SW0_RST_B_MDP_TDSHP0 6 +#define MT8167_MMSYS_SW0_RST_B_MDP_WDMA 7 +#define MT8167_MMSYS_SW0_RST_B_MDP_WROT0 8 +#define MT8167_MMSYS_SW0_RST_B_FAKE_ENG 9 +#define MT8167_MMSYS_SW0_RST_B_MUTEX 10 +#define MT8167_MMSYS_SW0_RST_B_DISP_OVL0 11 +#define MT8167_MMSYS_SW0_RST_B_DISP_RDMA0 12 +#define MT8167_MMSYS_SW0_RST_B_DISP_RDMA1 13 +#define MT8167_MMSYS_SW0_RST_B_DISP_WDMA0 14 +#define MT8167_MMSYS_SW0_RST_B_DISP_COLOR 15 +#define MT8167_MMSYS_SW0_RST_B_DISP_CCORR 16 +#define MT8167_MMSYS_SW0_RST_B_DISP_AAL 17 +#define MT8167_MMSYS_SW0_RST_B_DISP_GAMMA 18 +#define MT8167_MMSYS_SW0_RST_B_DISP_DITHER 19 +#define MT8167_MMSYS_SW0_RST_B_DISP_UFOE 20 +#define MT8167_MMSYS_SW0_RST_B_DISP_PWM 21 +#define MT8167_MMSYS_SW0_RST_B_DSI0 22 +#define MT8167_MMSYS_SW0_RST_B_DPI0 23 +#define MT8167_MMSYS_SW0_RST_B_MIPI_TX_CONFIG 24 +#define MT8167_MMSYS_SW1_RST_B_LVDS_ENCODER 25 +#define MT8167_MMSYS_SW1_RST_B_DPI1 26 +#define MT8167_MMSYS_SW1_RST_B_HDMI 27 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8167 */
--
2.43.0