[RFC PATCH 11/22] arm64: dts: ti: k3-j721s2-main: Add DDR nodes for J721S2
From: MANNURU VENKATESWARLU <hidden>
Date: 2026-07-14 12:56:38
Also in:
linux-devicetree
Subsystem:
arm/texas instruments k3 architecture, the rest · Maintainers:
Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Linus Torvalds
From: Neha Malcom Francis <redacted> Add DT nodes for the 2 DDR controllers on the J721S2 device. These define the memory controller with its register regions, interrupts, power domains, and clock requirements. This allows for DDR controller temperature monitoring. Signed-off-by: Neha Malcom Francis <redacted> Signed-off-by: MANNURU VENKATESWARLU <redacted> --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 84 ++++++++++++++++++++++ 1 file changed, 84 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 1228ac5711bf0..c8de5b74b97b6 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi@@ -37,6 +37,89 @@ l3cache-sram@200000 { }; }; + msmc0: msmc { + compatible = "ti,j721s2-msmc", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + intrlv-gran = <0>; + intrlv-size = <0>; + ecc-enable = <0>; + emif-config = <0>; + emif-active = <0>; + bootph-pre-ram; + + memorycontroller0: memorycontroller@2980000 { + compatible = "ti,j721s2-ddrss"; + reg = <0x0 0x02990000 0x0 0x4000>, + <0x0 0x0114000 0x0 0x100>, + <0x0 0x02980000 0x0 0x200>; + reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg"; + power-domains = <&k3_pds 138 TI_SCI_PD_SHARED>, + <&k3_pds 96 TI_SCI_PD_SHARED>; + interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x0000 0x00 0x02990000 0x00 0x4000>; + ti,ddr-freq0 = <0>; + ti,ddr-freq1 = <0>; + ti,ddr-freq2 = <0>; + ti,ddr-fhs-cnt = <0>; + clocks = <&k3_clks 138 0>, <&k3_clks 43 2>; + instance = <0>; + bootph-pre-ram; + + ddr0: ddr@0 { + compatible = "cdns,k3-ddr"; + reg = <0x00 0x0000 0x00 0x72c>, + <0x00 0x2000 0x00 0x4b0>, + <0x00 0x4000 0x00 0x163c>; + reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy"; + bootph-pre-ram; + }; + + ddr_pmu0: ddr-pmu@100 { + compatible = "ti,k3-ddr-pmu"; + reg = <0x00 0x100 0x00 0x14>; + }; + }; + + memorycontroller1: memorycontroller@29a0000 { + compatible = "ti,j721s2-ddrss"; + reg = <0x0 0x029b0000 0x0 0x4000>, + <0x0 0x0114000 0x0 0x100>, + <0x0 0x029a0000 0x0 0x200>; + reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg"; + power-domains = <&k3_pds 139 TI_SCI_PD_SHARED>, + <&k3_pds 97 TI_SCI_PD_SHARED>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x0000 0x00 0x029b0000 0x00 0x4000>; + ti,ddr-freq0 = <0>; + ti,ddr-freq1 = <0>; + ti,ddr-freq2 = <0>; + ti,ddr-fhs-cnt = <0>; + clocks = <&k3_clks 139 0>, <&k3_clks 43 2>; + instance = <1>; + bootph-pre-ram; + + ddr1: ddr@0 { + compatible = "cdns,k3-ddr"; + reg = <0x00 0x0000 0x00 0x72c>, + <0x00 0x2000 0x00 0x4b0>, + <0x00 0x4000 0x00 0x163c>; + reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy"; + bootph-pre-ram; + }; + + ddr_pmu1: ddr-pmu@100 { + compatible = "ti,k3-ddr-pmu"; + reg = <0x00 0x100 0x00 0x14>; + }; + }; + }; + scm_conf: bus@104000 { compatible = "simple-bus"; #address-cells = <1>;
@@ -2247,4 +2330,5 @@ mcasp4: mcasp@2b40000 { power-domains = <&k3_pds 213 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; + };
--
2.34.1