[PATCH v3 10/12] phy: phy-mtk-dp: Add bitrate register val definitions to SoC data
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Date: 2026-07-07 15:43:00
Also in:
dri-devel, linux-devicetree, linux-mediatek, linux-phy, lkml
Subsystem:
arm/mediatek usb3 phy driver, drm drivers for mediatek, generic phy framework, the rest · Maintainers:
Chunfeng Yun, Chun-Kuang Hu, Philipp Zabel, Vinod Koul, Linus Torvalds
In preparation for adding support for the eDP PHY found in newer SoCs, transfer the bitrate register value definitions to SoC specific data. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- drivers/phy/mediatek/phy-mtk-dp.c | 36 +++++++++++++++++++++++-------- 1 file changed, 27 insertions(+), 9 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-mtk-dp.c
index df193c712c77..4603f28d1466 100644
--- a/drivers/phy/mediatek/phy-mtk-dp.c
+++ b/drivers/phy/mediatek/phy-mtk-dp.c@@ -44,10 +44,6 @@ /* DP_PHYD_BIT_RATE */ #define PHYD_DIG_RG_BIT_RATE GENMASK(1, 0) -# define BIT_RATE_RBR 0 -# define BIT_RATE_HBR 1 -# define BIT_RATE_HBR2 2 -# define BIT_RATE_HBR3 3 /* DP_PHYD_SW_RST */ #define PHYD_DIG_GLB_SW_RST_B GENMASK(7, 0)
@@ -163,6 +159,14 @@ enum mtk_dp_phyd_dig_glb_regidx { DP_PHYD_GLOBAL_MAX }; +enum mtk_dp_phyd_bit_rate_regval { + DP_PHYD_BIT_RATE_RBR, + DP_PHYD_BIT_RATE_HBR, + DP_PHYD_BIT_RATE_HBR2, + DP_PHYD_BIT_RATE_HBR3, + DP_PHYD_BIT_RATE_MAX, +}; + static const u8 mt8195_phy_ana_glb_regs[DP_PHYA_GLOBAL_MAX] = { [DP_PHYA_GLB_BIAS_GEN_0] = 0x0, [DP_PHYA_GLB_BIAS_GEN_1] = 0x4,
@@ -189,6 +193,13 @@ static const u8 mt8195_phy_dig_glb_regs[DP_PHYD_GLOBAL_MAX] = { [DP_PHYD_TX_CTL_0] = 0x44, }; +static const u8 mt8195_phy_dig_bitrate_val[DP_PHYD_BIT_RATE_MAX] = { + [DP_PHYD_BIT_RATE_RBR] = 0, + [DP_PHYD_BIT_RATE_HBR] = 1, + [DP_PHYD_BIT_RATE_HBR2] = 2, + [DP_PHYD_BIT_RATE_HBR3] = 3 +}; + /** * struct mtk_dp_phya_imp_sel - Per-Lane Impedance Selection * @pmos: Impedance selection for P-Channel MOSFET
@@ -209,6 +220,7 @@ struct mtk_dp_phya_imp_sel { * @regs_ana_lane: Register (layout) offsets for ana_lan * @regs_dig_glb: Register (layout) offsets for dig_glb * @regs_dig_lane: Register (layout) offsets for dig_lan + * @val_dig_bitrate:IP Version specific register values for Bit Rate setting * @ana_bias_r: Internal resistance "R" Selection Settings (global) * @ana_cktx_imp: TX Clock Impedance Selection Settings (global) * @ana_lanes_imp: TX Impedance Selection Settings (for all lanes)
@@ -227,6 +239,9 @@ struct mtk_dp_phy_pdata { const u8 *regs_dig_glb; const u8 *regs_dig_lane; + /* IP-Version specific register value arrays */ + const u8 *val_dig_bitrate; + /* Calibration defaults */ u8 ana_bias_r; u8 ana_cktx_imp;
@@ -332,6 +347,7 @@ static int mtk_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) if (opts->dp.set_rate) { const u32 reg_bit_rate = pdata->regs_dig_glb[DP_PHYD_BIT_RATE]; + enum mtk_dp_phyd_bit_rate_regval regval_idx; switch (opts->dp.link_rate) { default:
@@ -340,19 +356,20 @@ static int mtk_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) opts->dp.link_rate); return -EINVAL; case 1620: - val = BIT_RATE_RBR; + regval_idx = DP_PHYD_BIT_RATE_RBR; break; case 2700: - val = BIT_RATE_HBR; + regval_idx = DP_PHYD_BIT_RATE_HBR; break; case 5400: - val = BIT_RATE_HBR2; + regval_idx = DP_PHYD_BIT_RATE_HBR2; break; case 8100: - val = BIT_RATE_HBR3; + regval_idx = DP_PHYD_BIT_RATE_HBR3; break; } - regmap_write(dp_phy->regmap, pdata->off_dig_glb + reg_bit_rate, val); + regmap_write(dp_phy->regmap, pdata->off_dig_glb + reg_bit_rate, + pdata->val_dig_bitrate[regval_idx]); } if (opts->dp.set_lanes) {
@@ -763,6 +780,7 @@ static const struct mtk_dp_phy_pdata mt8195_dp_phy_data = { .regs_ana_lane = mt8195_phy_ana_lane_regs, .regs_dig_glb = mt8195_phy_dig_glb_regs, .regs_dig_lane = mt8195_phy_dig_lane_regs, + .val_dig_bitrate = mt8195_phy_dig_bitrate_val, .ana_bias_r = 15, .ana_cktx_imp = 8, .ana_lanes_imp = {
--
2.54.0