[PATCH v2 09/12] phy: phy-mtk-dp: Rewrite and document default driving param macros
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Date: 2026-07-07 14:20:02
Also in:
dri-devel, linux-devicetree, linux-mediatek, linux-phy, lkml
Subsystem:
arm/mediatek usb3 phy driver, drm drivers for mediatek, generic phy framework, the rest · Maintainers:
Chunfeng Yun, Chun-Kuang Hu, Philipp Zabel, Vinod Koul, Linus Torvalds
Use FIELD_PREP_CONST and add nicer definitions/macros to build the default driving parameters for the PHY and, while at it, also add comments explaining what they are supposed to set in the PHY. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- drivers/phy/mediatek/phy-mtk-dp.c | 86 +++++++++++++++---------------- 1 file changed, 41 insertions(+), 45 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-mtk-dp.c
index d0ef8e8f6670..9a800d6b91c3 100644
--- a/drivers/phy/mediatek/phy-mtk-dp.c
+++ b/drivers/phy/mediatek/phy-mtk-dp.c@@ -85,51 +85,47 @@ * [2,5,8]: Swing 2 Pre1 and Swing 3 Pre0 */ #define PHYD_DIG_NUM_DRV_PARA_REGS 9 -#define XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT BIT(4) -#define XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT (BIT(10) | BIT(12)) -#define XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT GENMASK(20, 19) -#define XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT GENMASK(29, 29) -#define MT8195_DRIVING_PARAM_3_DEFAULT (XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT | \ - XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT | \ - XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT | \ - XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT) - -#define XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT GENMASK(4, 3) -#define XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT GENMASK(12, 9) -#define XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT (BIT(18) | BIT(21)) -#define XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT GENMASK(29, 29) -#define MT8195_DRIVING_PARAM_4_DEFAULT (XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT | \ - XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT | \ - XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT | \ - XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT) - -#define XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT (BIT(3) | BIT(5)) -#define XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT GENMASK(13, 12) -#define MT8195_DRIVING_PARAM_5_DEFAULT (XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT | \ - XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT) - -#define XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT 0 -#define XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT GENMASK(10, 10) -#define XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT GENMASK(19, 19) -#define XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT GENMASK(28, 28) -#define MT8195_DRIVING_PARAM_6_DEFAULT (XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT | \ - XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT | \ - XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT | \ - XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT) - -#define XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT 0 -#define XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT GENMASK(10, 9) -#define XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT GENMASK(19, 18) -#define XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT 0 -#define MT8195_DRIVING_PARAM_7_DEFAULT (XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT | \ - XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT | \ - XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT | \ - XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT) - -#define XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT GENMASK(3, 3) -#define XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT 0 -#define MT8195_DRIVING_PARAM_8_DEFAULT (XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT | \ - XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT) +#define XTP_LN_TX_LCTXC_SW0_PRE0 GENMASK(5, 0) +#define XTP_LN_TX_LCTXC_SW0_PRE1 GENMASK(13, 8) +#define XTP_LN_TX_LCTXC_SW0_PRE2 GENMASK(21, 16) +#define XTP_LN_TX_LCTXC_SW0_PRE3 GENMASK(29, 24) + +#define XTP_LN_TX_LCTXC_SW1_PRE0 GENMASK(5, 0) +#define XTP_LN_TX_LCTXC_SW1_PRE1 GENMASK(13, 8) +#define XTP_LN_TX_LCTXC_SW1_PRE2 GENMASK(21, 16) +#define XTP_LN_TX_LCTXC_SW2_PRE0 GENMASK(29, 24) + +#define XTP_LN_TX_LCTXC_SW2_PRE1 GENMASK(5, 0) +#define XTP_LN_TX_LCTXC_SW3_PRE0 GENMASK(13, 8) + +#define BUILD_DRIVING_PARAM_0(sw0_pre0, sw0_pre1, sw0_pre2, sw0_pre3) ( \ + FIELD_PREP_CONST(XTP_LN_TX_LCTXC_SW0_PRE0, sw0_pre0) | \ + FIELD_PREP_CONST(XTP_LN_TX_LCTXC_SW0_PRE1, sw0_pre1) | \ + FIELD_PREP_CONST(XTP_LN_TX_LCTXC_SW0_PRE2, sw0_pre2) | \ + FIELD_PREP_CONST(XTP_LN_TX_LCTXC_SW0_PRE3, sw0_pre3) \ +) + +#define BUILD_DRIVING_PARAM_12(sw1_pre0, sw1_pre1, sw1_pre2, sw2_pre0) (\ + FIELD_PREP_CONST(XTP_LN_TX_LCTXC_SW1_PRE0, sw1_pre0) | \ + FIELD_PREP_CONST(XTP_LN_TX_LCTXC_SW1_PRE1, sw1_pre1) | \ + FIELD_PREP_CONST(XTP_LN_TX_LCTXC_SW1_PRE2, sw1_pre2) | \ + FIELD_PREP_CONST(XTP_LN_TX_LCTXC_SW2_PRE0, sw2_pre0) \ +) + +#define BUILD_DRIVING_PARAM_23(sw2_pre1, sw3_pre0) ( \ + FIELD_PREP_CONST(XTP_LN_TX_LCTXC_SW2_PRE1, sw2_pre1) | \ + FIELD_PREP_CONST(XTP_LN_TX_LCTXC_SW3_PRE0, sw3_pre0) \ +) + +/* MT8195: Logic State Change Point (LC TX C) */ +#define MT8195_DRIVING_PARAM_3_DEFAULT BUILD_DRIVING_PARAM_0( 16, 20, 24, 32) +#define MT8195_DRIVING_PARAM_4_DEFAULT BUILD_DRIVING_PARAM_12(24, 30, 36, 32) +#define MT8195_DRIVING_PARAM_5_DEFAULT BUILD_DRIVING_PARAM_23(40, 48) + +/* MT8195: Positive Edge (LC TX CP) */ +#define MT8195_DRIVING_PARAM_6_DEFAULT BUILD_DRIVING_PARAM_0( 0, 4, 8, 16) +#define MT8195_DRIVING_PARAM_7_DEFAULT BUILD_DRIVING_PARAM_12(0, 6, 12, 0) +#define MT8195_DRIVING_PARAM_8_DEFAULT BUILD_DRIVING_PARAM_23(8, 0) enum mtk_dp_phya_ana_glb_regidx { DP_PHYA_GLB_BIAS_GEN_0,
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2.54.0