Re: [PATCH 1/8] drm/msm/a6xx: Fix RBBM_CLOCK_CNTL3_TP0 value in a730_hwcg
From: Konrad Dybcio <hidden>
Date: 2026-07-06 08:48:48
Also in:
dri-devel, linux-arm-msm, linux-devicetree, linux-iommu, lkml
On 7/5/26 10:14 AM, Akhil P Oommen wrote:
From: Puranam V G Tejaswi <redacted>
The RBBM_CLOCK_CNTL3_TP0 entry in a730_hwcg has bits[19:16] set to 2
(clock gating enabled for that TP0 stage). As per the latest
recommendation, clear this nibble to disable clock gating for this
particular stage.
Fixes: 9588d2f860a4 ("drm/msm/a6xx: Add A730 support")
Signed-off-by: Puranam V G Tejaswi <redacted>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---Reviewed-by: Konrad Dybcio <redacted> Konrad