[PATCH v2 3/4] arm64: Sort registers in cpu-feature-registers.rst
From: Mark Brown <broonie@kernel.org>
Date: 2026-07-02 19:12:05
Also in:
linux-doc, lkml
Subsystem:
arm64 port (aarch64 architecture), documentation, the rest · Maintainers:
Catalin Marinas, Will Deacon, Jonathan Corbet, Linus Torvalds
In order to make it a bit easier to work with sort the list of registers in cpu-feature-registers.rst lexically. There should be no content changes resulting from this patch. Signed-off-by: Mark Brown <broonie@kernel.org> --- Documentation/arch/arm64/cpu-feature-registers.rst | 223 +++++++++++---------- 1 file changed, 112 insertions(+), 111 deletions(-)
diff --git a/Documentation/arch/arm64/cpu-feature-registers.rst b/Documentation/arch/arm64/cpu-feature-registers.rst
index 4b10980d4a40..683bdd90c705 100644
--- a/Documentation/arch/arm64/cpu-feature-registers.rst
+++ b/Documentation/arch/arm64/cpu-feature-registers.rst@@ -170,137 +170,161 @@ infrastructure: +------------------------------+---------+---------+ - ID_AA64PFR0_EL1 - Processor Feature Register 0 + ID_AA64ISAR1_EL1 - Instruction set attribute register 1 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ - | DIT | [51-48] | y | + | LS64 | [63-60] | y | +------------------------------+---------+---------+ - | MPAM | [43-40] | n | + | I8MM | [55-52] | y | +------------------------------+---------+---------+ - | SVE | [35-32] | y | + | DGH | [51-48] | y | +------------------------------+---------+---------+ - | GIC | [27-24] | n | + | BF16 | [47-44] | y | +------------------------------+---------+---------+ - | AdvSIMD | [23-20] | y | + | SB | [39-36] | y | +------------------------------+---------+---------+ - | FP | [19-16] | y | + | FRINTTS | [35-32] | y | +------------------------------+---------+---------+ - | EL3 | [15-12] | n | + | GPI | [31-28] | y | +------------------------------+---------+---------+ - | EL2 | [11-8] | n | + | GPA | [27-24] | y | +------------------------------+---------+---------+ - | EL1 | [7-4] | n | + | LRCPC | [23-20] | y | +------------------------------+---------+---------+ - | EL0 | [3-0] | n | + | FCMA | [19-16] | y | + +------------------------------+---------+---------+ + | JSCVT | [15-12] | y | + +------------------------------+---------+---------+ + | API | [11-8] | y | + +------------------------------+---------+---------+ + | APA | [7-4] | y | + +------------------------------+---------+---------+ + | DPB | [3-0] | y | +------------------------------+---------+---------+ - - ID_AA64PFR1_EL1 - Processor Feature Register 1 + ID_AA64ISAR2_EL1 - Instruction set attribute register 2 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ - | GCS | [47-44] | y | + | LUT | [59-56] | y | +------------------------------+---------+---------+ - | SME | [27-24] | y | + | CSSC | [55-52] | y | +------------------------------+---------+---------+ - | MTE | [11-8] | y | + | RPRFM | [51-48] | y | +------------------------------+---------+---------+ - | SSBS | [7-4] | y | + | BC | [23-20] | y | +------------------------------+---------+---------+ - | BT | [3-0] | y | + | MOPS | [19-16] | y | + +------------------------------+---------+---------+ + | APA3 | [15-12] | y | + +------------------------------+---------+---------+ + | GPA3 | [11-8] | y | + +------------------------------+---------+---------+ + | RPRES | [7-4] | y | + +------------------------------+---------+---------+ + | WFXT | [3-0] | y | +------------------------------+---------+---------+ - ID_AA64PFR2_EL1 - Processor Feature Register 2 + ID_AA64ISAR3_EL1 - Instruction set attribute register 3 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ - | FPMR | [35-32] | y | + | FPRCVT | [31-28] | y | +------------------------------+---------+---------+ - | MTEFAR | [11-8] | y | + | LSFE | [19-16] | y | +------------------------------+---------+---------+ - | MTESTOREONLY | [7-4] | y | + | FAMINMAX | [7-4] | y | +------------------------------+---------+---------+ - MIDR_EL1 - Main ID Register + ID_AA64MMFR0_EL1 - Memory model feature register 0 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ - | Implementer | [31-24] | y | - +------------------------------+---------+---------+ - | Variant | [23-20] | y | + | ECV | [63-60] | y | +------------------------------+---------+---------+ - | Architecture | [19-16] | y | + + ID_AA64MMFR1_EL1 - Memory model feature register 1 + +------------------------------+---------+---------+ - | PartNum | [15-4] | y | + | Name | bits | visible | +------------------------------+---------+---------+ - | Revision | [3-0] | y | + | AFP | [47-44] | y | +------------------------------+---------+---------+ - NOTE: The 'visible' fields of MIDR_EL1 will contain the value - as available on the CPU where it is fetched and is not a system - wide safe value. - - ID_AA64ISAR1_EL1 - Instruction set attribute register 1 + ID_AA64MMFR2_EL1 - Memory model feature register 2 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ - | LS64 | [63-60] | y | + | AT | [35-32] | y | +------------------------------+---------+---------+ - | I8MM | [55-52] | y | + + ID_AA64MMFR3_EL1 - Memory model feature register 3 + +------------------------------+---------+---------+ - | DGH | [51-48] | y | + | Name | bits | visible | +------------------------------+---------+---------+ - | BF16 | [47-44] | y | + | S1POE | [19-16] | y | +------------------------------+---------+---------+ - | SB | [39-36] | y | + + ID_AA64PFR0_EL1 - Processor Feature Register 0 + +------------------------------+---------+---------+ - | FRINTTS | [35-32] | y | + | Name | bits | visible | +------------------------------+---------+---------+ - | GPI | [31-28] | y | + | DIT | [51-48] | y | +------------------------------+---------+---------+ - | GPA | [27-24] | y | + | MPAM | [43-40] | n | +------------------------------+---------+---------+ - | LRCPC | [23-20] | y | + | SVE | [35-32] | y | +------------------------------+---------+---------+ - | FCMA | [19-16] | y | + | GIC | [27-24] | n | +------------------------------+---------+---------+ - | JSCVT | [15-12] | y | + | AdvSIMD | [23-20] | y | +------------------------------+---------+---------+ - | API | [11-8] | y | + | FP | [19-16] | y | +------------------------------+---------+---------+ - | APA | [7-4] | y | + | EL3 | [15-12] | n | +------------------------------+---------+---------+ - | DPB | [3-0] | y | + | EL2 | [11-8] | n | + +------------------------------+---------+---------+ + | EL1 | [7-4] | n | + +------------------------------+---------+---------+ + | EL0 | [3-0] | n | +------------------------------+---------+---------+ - ID_AA64MMFR0_EL1 - Memory model feature register 0 + + ID_AA64PFR1_EL1 - Processor Feature Register 1 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ - | ECV | [63-60] | y | + | GCS | [47-44] | y | +------------------------------+---------+---------+ - - ID_AA64MMFR2_EL1 - Memory model feature register 2 - + | SME | [27-24] | y | +------------------------------+---------+---------+ - | Name | bits | visible | + | MTE | [11-8] | y | +------------------------------+---------+---------+ - | AT | [35-32] | y | + | SSBS | [7-4] | y | + +------------------------------+---------+---------+ + | BT | [3-0] | y | +------------------------------+---------+---------+ - ID_AA64MMFR3_EL1 - Memory model feature register 3 + ID_AA64PFR2_EL1 - Processor Feature Register 2 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ - | S1POE | [19-16] | y | + | FPMR | [35-32] | y | + +------------------------------+---------+---------+ + | MTEFAR | [11-8] | y | + +------------------------------+---------+---------+ + | MTESTOREONLY | [7-4] | y | +------------------------------+---------+---------+ ID_AA64SMFR0_EL1 - SME feature ID register 0
@@ -387,50 +411,64 @@ infrastructure: | SVEVer | [3-0] | y | +------------------------------+---------+---------+ - ID_AA64MMFR1_EL1 - Memory model feature register 1 + ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ - | AFP | [47-44] | y | + | CRC32 | [19-16] | y | + +------------------------------+---------+---------+ + | SHA2 | [15-12] | y | + +------------------------------+---------+---------+ + | SHA1 | [11-8] | y | + +------------------------------+---------+---------+ + | AES | [7-4] | y | +------------------------------+---------+---------+ - ID_AA64ISAR2_EL1 - Instruction set attribute register 2 + ID_ISAR6_EL1 - AArch32 Instruction Set Attribute Register 6 +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ - | LUT | [59-56] | y | - +------------------------------+---------+---------+ - | CSSC | [55-52] | y | + | I8MM | [27-24] | y | +------------------------------+---------+---------+ - | RPRFM | [51-48] | y | + | BF16 | [23-20] | y | +------------------------------+---------+---------+ - | BC | [23-20] | y | + | SB | [15-12] | y | +------------------------------+---------+---------+ - | MOPS | [19-16] | y | + | FHM | [11-8] | y | +------------------------------+---------+---------+ - | APA3 | [15-12] | y | + | DP | [7-4] | y | +------------------------------+---------+---------+ - | GPA3 | [11-8] | y | + + ID_PFR2_EL1 - AArch32 Processor Feature Register 2 + +------------------------------+---------+---------+ - | RPRES | [7-4] | y | + | Name | bits | visible | +------------------------------+---------+---------+ - | WFXT | [3-0] | y | + | SSBS | [7-4] | y | +------------------------------+---------+---------+ - ID_AA64ISAR3_EL1 - Instruction set attribute register 3 + MIDR_EL1 - Main ID Register +------------------------------+---------+---------+ | Name | bits | visible | +------------------------------+---------+---------+ - | FPRCVT | [31-28] | y | + | Implementer | [31-24] | y | +------------------------------+---------+---------+ - | LSFE | [19-16] | y | + | Variant | [23-20] | y | +------------------------------+---------+---------+ - | FAMINMAX | [7-4] | y | + | Architecture | [19-16] | y | + +------------------------------+---------+---------+ + | PartNum | [15-4] | y | + +------------------------------+---------+---------+ + | Revision | [3-0] | y | +------------------------------+---------+---------+ + NOTE: The 'visible' fields of MIDR_EL1 will contain the value + as available on the CPU where it is fetched and is not a system + wide safe value. + MVFR0_EL1 - AArch32 Media and VFP Feature Register 0 +------------------------------+---------+---------+
@@ -457,43 +495,6 @@ infrastructure: | SIMDLS | [11-8] | y | +------------------------------+---------+---------+ - ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5 - - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | CRC32 | [19-16] | y | - +------------------------------+---------+---------+ - | SHA2 | [15-12] | y | - +------------------------------+---------+---------+ - | SHA1 | [11-8] | y | - +------------------------------+---------+---------+ - | AES | [7-4] | y | - +------------------------------+---------+---------+ - - ID_ISAR6_EL1 - AArch32 Instruction Set Attribute Register 6 - - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | I8MM | [27-24] | y | - +------------------------------+---------+---------+ - | BF16 | [23-20] | y | - +------------------------------+---------+---------+ - | SB | [15-12] | y | - +------------------------------+---------+---------+ - | FHM | [11-8] | y | - +------------------------------+---------+---------+ - | DP | [7-4] | y | - +------------------------------+---------+---------+ - - ID_PFR2_EL1 - AArch32 Processor Feature Register 2 - - +------------------------------+---------+---------+ - | Name | bits | visible | - +------------------------------+---------+---------+ - | SSBS | [7-4] | y | - +------------------------------+---------+---------+ Appendix I: Example -------------------
--
2.47.3