[PATCH v13 02/15] arm64: barrier: Support smp_cond_load_relaxed_timeout()
From: Ankur Arora <hidden>
Date: 2026-07-02 01:34:21
Also in:
bpf, linux-arch, linux-pm, lkml
Subsystem:
arm64 port (aarch64 architecture), the rest · Maintainers:
Catalin Marinas, Will Deacon, Linus Torvalds
Support waiting in smp_cond_load_relaxed_timeout() via __cmpwait_relaxed(). To ensure that we wake from waiting in WFE periodically and don't block forever if there are no stores to ptr, this path is only used when the event-stream is enabled. Note that when using __cmpwait_relaxed() we ignore the timeout value, allowing an overshoot by up to the event-stream period. And, in the unlikely event that the event-stream is unavailable, fallback to spin-waiting. Also set SMP_TIMEOUT_POLL_COUNT to 1 so we do the time-check in each iteration of smp_cond_load_relaxed_timeout(). Note that with this we have enough to define ARCH_HAS_CPU_RELAX to indicate that we support an optimized implementation of cpu_poll_relax(). However, defer defining ARCH_HAS_CPU_RELAX as that enables polling based C-state handling, which really needs TIF_POLLING_NRFLAG. Cc: Arnd Bergmann <arnd@arndb.de> Cc: Will Deacon <will@kernel.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: linux-arm-kernel@lists.infradead.org Suggested-by: Will Deacon <will@kernel.org> Acked-by: Will Deacon <will@kernel.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Ankur Arora <redacted> --- Notes: remove definition of ARCH_HAS_CPU_RELAX as that adds a degenerate implementation of polling in idle via acpi_processor_setup_cstates(). Flagged by BPF bot [1]. Will, Catalin: I've retained your ack and r-by tags. Hope that's okay. As mentioned in the prior patch, not addressing the range comment [2]. [1] https://lore.kernel.org/all/23edac0734ee3ef334237165500d8f34e3c649081db7b3140a4a8596a202f339@mail.kernel.org/ (local) [2] https://lore.kernel.org/all/20260608083135.6C0C81F00893@smtp.kernel.org/ (local) -- arch/arm64/include/asm/barrier.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)
diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h
index 9495c4441a46..6190e178db51 100644
--- a/arch/arm64/include/asm/barrier.h
+++ b/arch/arm64/include/asm/barrier.h@@ -12,6 +12,7 @@ #include <linux/kasan-checks.h> #include <asm/alternative-macros.h> +#include <asm/vdso/processor.h> #define __nops(n) ".rept " #n "\nnop\n.endr\n" #define nops(n) asm volatile(__nops(n))
@@ -219,6 +220,26 @@ do { \ (typeof(*ptr))VAL; \ }) +/* Re-declared here to avoid include dependency. */ +extern bool arch_timer_evtstrm_available(void); + +/* + * In the common case, cpu_poll_relax() sits waiting in __cmpwait_relaxed() + * for the ptr value to change. + * + * Since this period is reasonably long, choose SMP_TIMEOUT_POLL_COUNT + * to be 1, so smp_cond_load_{relaxed,acquire}_timeout() does a + * time-check in each iteration. + */ +#define SMP_TIMEOUT_POLL_COUNT 1 + +#define cpu_poll_relax(ptr, val, timeout_ns) do { \ + if (arch_timer_evtstrm_available()) \ + __cmpwait_relaxed(ptr, val); \ + else \ + cpu_relax(); \ +} while (0) + #include <asm-generic/barrier.h> #endif /* __ASSEMBLER__ */
--
2.43.7