[PATCH v2 3/5] arm64: dts: ls1046a: describe the Lynx 10G SerDes blocks
From: Ioana Ciornei <ioana.ciornei@nxp.com>
Date: 2026-07-01 13:11:55
Also in:
imx, linux-devicetree, lkml
Subsystem:
arm/freescale layerscape arm architecture, the rest · Maintainers:
Frank Li, Linus Torvalds
From: Vladimir Oltean <vladimir.oltean@nxp.com> Describe the two Lynx 10G SerDes blocks and their associated lanes found on the LS1046A SoC. The nodes are left disabled at the SoC level; board DTs will be expected to enable them once the consumer Ethernet nodes appear. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> --- Changes in v2: - Change the size of the region to 0x2000 --- .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 6fefe837f434..270a97711a69 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi@@ -424,6 +424,66 @@ sfp: efuse@1e80000 { clock-names = "sfp"; }; + serdes1: phy@1ea0000 { + compatible = "fsl,ls1046a-serdes1"; + reg = <0x00 0x1ea0000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; + #phy-cells = <1>; + big-endian; + status = "disabled"; + + serdes1_lane_a: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + serdes1_lane_b: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + serdes1_lane_c: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + + serdes1_lane_d: phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + }; + + serdes2: phy@1eb0000 { + compatible = "fsl,ls1046a-serdes2"; + reg = <0x00 0x1eb0000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; + #phy-cells = <1>; + big-endian; + status = "disabled"; + + serdes2_lane_a: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + serdes2_lane_b: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + serdes2_lane_c: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + + serdes2_lane_d: phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + }; + dcfg: dcfg@1ee0000 { compatible = "fsl,ls1046a-dcfg", "syscon"; reg = <0x0 0x1ee0000 0x0 0x1000>;
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2.25.1