[PATCH 12/12] phy: phy-mtk-dp: Add support for MT8196 eDP PHY
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Date: 2026-07-01 12:20:26
Also in:
dri-devel, linux-devicetree, linux-mediatek, linux-phy, lkml
Subsystem:
arm/mediatek usb3 phy driver, drm drivers for mediatek, generic phy framework, the rest · Maintainers:
Chunfeng Yun, Chun-Kuang Hu, Philipp Zabel, Vinod Koul, Linus Torvalds
The MT8196 SoC features an updated PHY IP compared to the older ones, and there is one that is specific to Embedded DisplayPort. Add support for the eDP PHY found in the MediaTek MT8196 SoC and all of its variants. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- drivers/phy/mediatek/phy-mtk-dp.c | 66 ++++++++++++++++++++++++++++++- 1 file changed, 65 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-mtk-dp.c
index 2c402b416683..c8abc4a2af0a 100644
--- a/drivers/phy/mediatek/phy-mtk-dp.c
+++ b/drivers/phy/mediatek/phy-mtk-dp.c@@ -5,7 +5,7 @@ * Copyright (c) 2022, BayLibre Inc. * Copyright (c) 2022, MediaTek Inc. * - * Major refactoring + * Major refactoring and new SoCs support * Copyright (c) 2026, Collabora Ltd. * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> */
@@ -41,6 +41,7 @@ #define TPLL_SSC_EN BIT(3) /* DP_PHYD_BIT_RATE */ +#define PHYD_DIG_RG_BIT_RATE_V2 GENMASK(3, 0) #define PHYD_DIG_RG_BIT_RATE GENMASK(1, 0) /* DP_PHYD_SW_RST */
@@ -57,6 +58,7 @@ /* DP_PHYD_TX_CTL_0 */ #define PHYD_TX_LN_EN GENMASK(7, 4) +#define PHYD_TX_LN_EN_V2 GENMASK(3, 0) /* DP_PHYD_DRIVING_FORCE */ #define PHYD_DP_TX_FORCE_VOLT_SWING_EN BIT(0)
@@ -123,6 +125,16 @@ #define MT8195_DRIVING_PARAM_7_DEFAULT BUILD_DRIVING_PARAM_12(0, 6, 12, 0) #define MT8195_DRIVING_PARAM_8_DEFAULT BUILD_DRIVING_PARAM_23(8, 0) +/* MT8196/MT6991: Logic State Change Point (LC TX C) */ +#define MT8196_DRIVING_PARAM_3_DEFAULT BUILD_DRIVING_PARAM_0( 10, 12, 14, 17) +#define MT8196_DRIVING_PARAM_4_DEFAULT BUILD_DRIVING_PARAM_12(14, 17, 18, 18) +#define MT8196_DRIVING_PARAM_5_DEFAULT BUILD_DRIVING_PARAM_23(21, 24) + +/* MT8196/MT6991: Positive Edge (LC TX CP) */ +#define MT8196_DRIVING_PARAM_6_DEFAULT BUILD_DRIVING_PARAM_0( 0, 2, 4, 7) +#define MT8196_DRIVING_PARAM_7_DEFAULT BUILD_DRIVING_PARAM_12(0, 3, 6, 0) +#define MT8196_DRIVING_PARAM_8_DEFAULT BUILD_DRIVING_PARAM_23(3, 0) + enum mtk_dp_phya_ana_glb_regidx { DP_PHYA_GLB_BIAS_GEN_0, DP_PHYA_GLB_BIAS_GEN_1,
@@ -178,6 +190,11 @@ static const u8 mt8195_phy_dig_lane_regs[DP_PHYD_LAN_MAX] = { [DP_PHYD_LAN_DRIVING_PARAM_0] = 0x2c, }; +static const u8 mt8196_phy_dig_lane_regs[DP_PHYD_LAN_MAX] = { + [DP_PHYD_LAN_DRIVING_FORCE] = 0x30, + [DP_PHYD_LAN_DRIVING_PARAM_0] = 0x2c, +}; + static const u8 mt8195_phy_dig_glb_regs[DP_PHYD_GLOBAL_MAX] = { [DP_PHYD_PLL_CTL_0] = 0x10, [DP_PHYD_PLL_CTL_1] = 0x14,
@@ -187,6 +204,15 @@ static const u8 mt8195_phy_dig_glb_regs[DP_PHYD_GLOBAL_MAX] = { [DP_PHYD_TX_CTL_0] = 0x44, }; +static const u8 mt8196_phy_dig_glb_regs[DP_PHYD_GLOBAL_MAX] = { + [DP_PHYD_PLL_CTL_0] = 0x10, + [DP_PHYD_PLL_CTL_1] = 0x14, + [DP_PHYD_SW_RST] = 0x38, + [DP_PHYD_BIT_RATE] = 0x3c, + [DP_PHYD_AUX_RX_CTL] = 0x40, + [DP_PHYD_TX_CTL_0] = 0x74, +}; + static const u8 mt8195_phy_dig_bitrate_val[DP_PHYD_BIT_RATE_MAX] = { [DP_PHYD_BIT_RATE_RBR] = 0, [DP_PHYD_BIT_RATE_HBR] = 1,
@@ -194,6 +220,13 @@ static const u8 mt8195_phy_dig_bitrate_val[DP_PHYD_BIT_RATE_MAX] = { [DP_PHYD_BIT_RATE_HBR3] = 3 }; +static const u8 mt8196_edp_phy_dig_bitrate_val[DP_PHYD_BIT_RATE_MAX] = { + [DP_PHYD_BIT_RATE_RBR] = 1, + [DP_PHYD_BIT_RATE_HBR] = 4, + [DP_PHYD_BIT_RATE_HBR2] = 7, + [DP_PHYD_BIT_RATE_HBR3] = 9 +}; + /** * struct mtk_dp_phya_imp_sel - Per-Lane Impedance Selection * @pmos: Impedance selection for P-Channel MOSFET
@@ -751,8 +784,39 @@ static const struct mtk_dp_phy_pdata mt8195_dp_phy_data = { }, }; +static const struct mtk_dp_phy_pdata mt8196_edp_phy_data = { + .off_ana_glb = 0x400, + .off_ana_lane = (const u16[]) { 0x0, 0x100, 0x200, 0x300 }, + .off_dig_glb = 0x1400, + .off_dig_lane = (const u16[]) { 0x1000, 0x1100, 0x1200, 0x1300 }, + .regs_ana_glb = mt8195_phy_ana_glb_regs, + .regs_ana_lane = mt8195_phy_ana_lane_regs, + .regs_dig_glb = mt8196_phy_dig_glb_regs, + .regs_dig_lane = mt8196_phy_dig_lane_regs, + .mask_dig_tx_ln = PHYD_TX_LN_EN_V2, + .val_dig_bitrate = mt8196_edp_phy_dig_bitrate_val, + .ana_bias_r = 15, + .ana_cktx_imp = 8, + .ana_lanes_imp = { + .pmos = 8, + .nmos = 8, + }, + .driving_params = (const u32[]) { + [0] = 0, + [1] = 0, + [2] = 0, + [3] = MT8196_DRIVING_PARAM_3_DEFAULT, + [4] = MT8196_DRIVING_PARAM_4_DEFAULT, + [5] = MT8196_DRIVING_PARAM_5_DEFAULT, + [6] = MT8196_DRIVING_PARAM_6_DEFAULT, + [7] = MT8196_DRIVING_PARAM_7_DEFAULT, + [8] = MT8196_DRIVING_PARAM_8_DEFAULT + }, +}; + static const struct of_device_id mtk_dp_phy_of_match[] = { { .compatible = "mediatek,mt8195-dp-phy", .data = &mt8195_dp_phy_data }, + { .compatible = "mediatek,mt8196-edp-phy", .data = &mt8196_edp_phy_data }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mtk_dp_phy_of_match);
--
2.54.0