[PATCH v2 1/2] dt-bindings: soc: xilinx: Add MYIR MYS-7Z020-V2 board
From: Liu Yu <hidden>
Date: 2026-06-19 13:24:57
Also in:
linux-devicetree
Subsystem:
arm/zynq architecture, open firmware and flattened device tree bindings, the rest · Maintainers:
Michal Simek, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
Add compatible string for the MYIR MYS-7Z020-V2 board, based on the Xilinx Zynq-7000 XC7Z020 SoC. Signed-off-by: Liu Yu <redacted> --- Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml | 1 + 1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
index c9f99e0df2b3..72a84b628da3 100644
--- a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
+++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml@@ -23,6 +23,7 @@ properties: - digilent,zynq-zybo - digilent,zynq-zybo-z7 - ebang,ebaz4205 + - myir,mys-7z020-v2 - myir,zynq-zturn-v5 - myir,zynq-zturn - xlnx,zynq-cc108
--
2.43.0