RE: [PATCH v4 3/5] dt-bindings: clock: cix,sky1-audss-clock: add audss clock controller
From: Joakim Zhang <hidden>
Date: 2026-06-18 09:28:02
Also in:
linux-clk, linux-devicetree, lkml
Hello,
-----Original Message----- From: Philipp Zabel <p.zabel@pengutronix.de> Sent: Thursday, June 18, 2026 4:30 PM To: Joakim Zhang <redacted>; Conor Dooley [off-list ref] Cc: mturquette@baylibre.com; sboyd@kernel.org; bmasney@redhat.com; robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org; Gary Yang [off-list ref]; cix-kernel-upstream <cix-kernel- upstream@cixtech.com>; linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm- kernel@lists.infradead.org Subject: Re: [PATCH v4 3/5] dt-bindings: clock: cix,sky1-audss-clock: add audss clock controller EXTERNAL EMAIL CAUTION: Suspicious Email from unusual domain. On Do, 2026-06-18 at 01:43 +0000, Joakim Zhang wrote:quoted
Hello,quoted
-----Original Message----- From: Conor Dooley <conor@kernel.org> Sent: Wednesday, June 17, 2026 11:56 PM To: Joakim Zhang <redacted> Cc: mturquette@baylibre.com; sboyd@kernel.org; bmasney@redhat.com; robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org; p.zabel@pengutronix.de; Gary Yang [off-list ref]; cix-kernel- upstream [off-list ref]; linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm- kernel@lists.infradead.org Subject: Re: [PATCH v4 3/5] dt-bindings: clock: cix,sky1-audss-clock: add audss clock controller On Wed, Jun 17, 2026 at 02:04:35PM +0800, joakim.zhang@cixtech.comwrote:quoted
quoted
quoted
From: Joakim Zhang <redacted> The AUDSS CRU contains an internal clock tree of muxes, dividers and gates for DSP, I2S, HDA, DMAC and related blocks. The clock provider is a child node of the cix,sky1-audss-system-control syscon and accesses registers through the parent MMIO region.Why can this not just be part of the parent syscon node?The clock and reset blocks are handled by different subsystems andmaintainers (clk vs reset). Putting the clock provider on the parent syscon node would mean a single driver has to register both the reset controller and the clock provider on one device, which doesn't fit well. There are many examples of clock and reset drivers sharing the same node, by using platform_driver for one (usually clk) and auxiliary_driver for the other (usually reset).
OK, I will have a look. If you are also prefer to this, I will refactor the patch. Thanks, Joakim