RE: [EXTERNAL] Re: [PATCH 3/3] dt-bindings: perf: marvell: Extend CN10K TAD PMU binding for CN20K

-----Original Message-----
From: Conor Dooley <conor@kernel.org>
Sent: Monday, June 8, 2026 11:05 PM
To: Geethasowjanya Akula <gakula@marvell.com>
Cc: linux-perf-users@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
kernel@lists.infradead.org; devicetree@vger.kernel.org;
mark.rutland@arm.com; will@kernel.org; krzk+dt@kernel.org
Subject: [EXTERNAL] Re: [PATCH 3/3] dt-bindings: perf: marvell: Extend CN10K
TAD PMU binding for CN20K

On Sun, Jun 07, 2026 at 06:21:01PM +0530, Geetha sowjanya wrote:

quoted

Allow marvell,cn20k-tad-pmu alongside marvell,cn10k-tad-pmu, document
CN20K in the title and description, add a maintainer, and include a
CN20K example node with the same required properties as CN10K.

This is great and all, but is evident from the diff (other than the fact it talks
about an example that does not exist).
What is missing is an explanation of why a fallback comaptible is not usable.

CN20K requires a distinct compatible because the PFC/PRF register offsets relative to each TAD base differ from CN10K, and these offsets are not described via DT properties.
In addition, CN20K introduces new events that are not supported on CN10K.
Due to these differences, using marvell,cn10k-tad-pmu as a fallback would result in incorrect configuration.
I will update the commit message in the next revision to clarify this.

Thanks,
Geetha

pw-bot: changes-requested

Thanks,
Conor.

quoted

Signed-off-by: Geetha sowjanya <gakula@marvell.com>
---
 .../bindings/perf/marvell-cn10k-tad.yaml      | 20 +++++++++++--------
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git
a/Documentation/devicetree/bindings/perf/marvell-cn10k-tad.yaml
b/Documentation/devicetree/bindings/perf/marvell-cn10k-tad.yaml
index 362142252667..1612052b59ae 100644

--- a/Documentation/devicetree/bindings/perf/marvell-cn10k-tad.yaml
+++ b/Documentation/devicetree/bindings/perf/marvell-cn10k-tad.yaml

@@ -4,23 +4,27 @@
 $id: http://devicetree.org/schemas/perf/marvell-cn10k-tad.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#

-title: Marvell CN10K LLC-TAD performance monitor
+title: Marvell CN10K / CN20K LLC-TAD performance monitor

 maintainers:
   - Bhaskara Budiredla <bbudiredla@marvell.com>
+  - Geetha sowjanya <gakula@marvell.com>

 description: |
-  The Tag-and-Data units (TADs) maintain coherence and contain CN10K
-  shared on-chip last level cache (LLC). The tad pmu measures the
-  performance of last-level cache. Each tad pmu supports up to eight
-  counters.
+  The Tag-and-Data units (TADs) maintain coherence and contain the
+ shared on-chip last level cache (LLC) on Marvell CN10K and CN20K SoCs.
+  The TAD PMU measures last-level cache performance. Each TAD PMU
+ supports up to eight counters.

-  The DT setup comprises of number of tad blocks, the sizes of pmu
-  regions, tad blocks and overall base address of the HW.
+  The DT setup describes the number of TAD blocks, the sizes of PMU
+ regions and TAD pages, and the overall MMIO base of the hardware.

 properties:
   compatible:
-    const: marvell,cn10k-tad-pmu
+    items:
+      - enum:
+          - marvell,cn10k-tad-pmu
+          - marvell,cn20k-tad-pmu

   reg:
     maxItems: 1
--

2.25.1