On Mon, Jun 01, 2026 at 10:53:38AM +0100, Suzuki K Poulose wrote:

On 19/05/2026 16:48, Yeoreum Yun wrote:

quoted

According to IHI006H Embedded Trace Macrocell Architecture
Specification [0], n could be 0-2 for TCRSEQEVR<n> when
TCRIDR5.NUMSEQSTATE is 0b100.

Therefore, introduce ETM_MAX_SEQ_TRANSITIONS macro and apply this
in TCRSEQEVR<n> relevant fields.

Link: https://developer.arm.com/documentation/ihi0064/latest/ [0]
Suggestedby: Leo Yan [off-list ref]
Signed-off-by: Yeoreum Yun <redacted>
---
  drivers/hwtracing/coresight/coresight-etm4x-cfg.c | 2 +-
  drivers/hwtracing/coresight/coresight-etm4x.h     | 5 +++--
  2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
index c302072b293a..e1a59b434505 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c

@@ -76,7 +76,7 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata,
  	} else if ((offset & GENMASK(11, 4)) == TRCSEQEVRn(0)) {
  		/* sequencer state control registers */
  		idx = (offset & GENMASK(3, 0)) / 4;
-		if (idx < ETM_MAX_SEQ_STATES) {
+		if (idx < ETM_MAX_SEQ_TRANSITIONS) {
  			reg_csdev->driver_regval = &drvcfg->seq_ctrl[idx];
  			err = 0;
  		}

diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 89d81ce4e04e..60e08ab085c5 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h

@@ -614,6 +614,7 @@ static inline u32 etm4_res_sel_pair(u8 res_sel_idx)
  #define ETM_MAX_NR_PE			8
  #define ETMv4_MAX_CNTR			4
  #define ETM_MAX_SEQ_STATES		4
+#define ETM_MAX_SEQ_TRANSITIONS		(ETM_MAX_SEQ_STATES - 1)

Similar to the other comment on the patch, please don't tie this to
SEQ_STATES. Simpl define.

#define ETM_MAX_SEQ_CTRLS		3

Okay. I'll untie them. Thanks!

[...]

-- 
Sincerely,
Yeoreum Yun